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FEOL (Front-End-Of-Line) Staff Process Integration Development Engineer image - Rise Careers
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FEOL (Front-End-Of-Line) Staff Process Integration Development Engineer

Job Details:

Job Description: 

Fab Sort Manufacturing (FSM) is responsible for producing all Intel silicon using advanced manufacturing processes in facilities across Arizona, Ireland, Israel, and Oregon. In alignment with Intel's IDM2.0 strategy, FSM is expanding operations to meet the demands of both internal and foundry customers, introducing state-of-the-art technologies into high-volume manufacturing. Intel has established the HVM Global Yield organization within FSM to enhance yield operations and facilitate rapid yield ramp-up during early high-volume manufacturing phases, collaborating with the Technology Development team and FSM Fab managers.

This job requisition seeks Front-End-Of-Line (FEOL) Process Integration engineers for the HVM Global Yield organization, reporting to the FEOL Process Integration manager. Selected candidates will collaborate with FEOL integration members, Global Yield teams, fab modules, and TD team members to optimize processes and achieve yield ramp-up in the early production stage, supporting both internal and external customers.

FEOL (Front-End-Of-Line) Integration Development Engineers are responsible for:

  • Leading engineering projects to execute high-volume manufacturing (HVM) yield roadmaps and achieve performance targets.

  • Collaborating with Technology Development and Local Yield teams to implement new technologies in production fabs.

  • Working with FEOL/BEOL Integration, Device, Defect Reduction, and Yield Analysis teams to identify root causes of yield and performance issues and executing mitigation plans within set timelines.

  • Conducting feasibility studies and experiments to characterize processes and enhance product performance throughout development.

  • Managing New Product Introductions (NPI) in production fabs and optimizing processes to meet foundry customer specifications.

  • Partnering with Local Yield teams to improve product yield, quality, performance, and reduce wafer costs.

Qualifications:

Minimum qualifications are required to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelor's degree in a relevant science or engineering field, with at least 8 years of experience.

  • Experience in advanced node semiconductor industry, specifically in FEOL Process Integration; level of experience will influence job grade.

  • Proficient understanding of Device Physics, with experience in FinFET or Gate-All-Around technology development or high-volume manufacturing.

  • Familiarity with module processes such as lithography, dry etch, wet etch, CMP, diffusion, implant, thin films, and metrology.

  • Strong problem-solving skills, self-initiative, and ability to learn independently.

  • Ability to collaborate effectively with multi-functional and multi-cultural teams.

  • Excellent communication skills.

Preferred Qualifications:

  • Advanced degree (Master's or Ph.D.) in Electrical Engineering, Physics, or Materials Science; related fields may be considered based on industry experience.

  • Experience in project/program management and/or as a TFT lead.

  • Strong interpersonal skills, including the ability to influence and motivate others.

  • Experience engaging with external foundry customers through technical interactions.

  • Familiarity with GAA (Gate-All-Around) technology architecture.

  • Background in new semiconductor technology development.

Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Ireland)

Primary Location: 

Ireland, Leixlip

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$115000 / YEARLY (est.)
min
max
$100000K
$130000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
April 3, 2025

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