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IP Micro Architect / RTL Logic Design Lead

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Job Details:

Job Description:

The DCAI and Silicon Eng Team deliver leadership Xeon products to cloud and datacenter customers through development of industry leading x86 core and differentiated IPs that enhances product performance and competitiveness in both Xeon and AI platforms. IP design group within DCAI designs Coherent Fabric IP, Memory controller, NOC, PCIE and many fundamental building blocks for the Xeon server SOCs.

We are seeking an experienced Senior Micro Architect to design, develop, and implement advanced Digital IO Controllers like PCIe/CXL/UCIe systems for next-generation data center and AI chips.

This role requires a unique blend of architectural expertise and hands-on RTL coding skills to bring cutting-edge designs to life.
The ideal candidate will have a deep understanding of high speed IOs like PCIe/CXL/UCIe architecture, interconnect protocols and coherence mechanisms, coupled with a proven ability to implement these designs at the RTL level.
Architect scalable memory coherency protocols and interconnect topologies to achieve high performance and low latency for data center and AI SoCs.
Design and implement critical components of the memory fabric microarchitecture, including coherency controllers and interconnect blocks.
Develop RTL code for core components of the memory fabric, ensuring optimal performance, area, and power trade-offs.
Work closely with verification teams to create test plans and debug issues arising during pre-silicon validation.
Collaborate with cross-functional teams (physical design, software, and firmware) to ensure seamless integration of memory fabric systems.
Analyze system performance, conduct workload modeling, and optimize the architecture for target use cases.
Mentor junior engineers and contribute to technical reviews and design documentation.
Stay updated with emerging technologies and trends in PCIe/CXL/UCIe protocols, and AI/ML hardware.
Strong problem-solving and debugging skills.
Excellent communication and collaboration abilities.
Ability to manage and prioritize multiple tasks effectively.

Qualifications:

Must have a Bachelor's degree with 15+ year experience or Master's degree in Electronics and Computer Engineering with relevant experience of at least 10+ years

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$160000 / YEARLY (est.)

min

max

$140000K

$180000K

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What You Should Know About IP Micro Architect / RTL Logic Design Lead, Intel

Join Intel as an IP Micro Architect / RTL Logic Design Lead in the vibrant tech hub of Bangalore, India! In this exciting position, you’ll be part of the DCAI and Silicon Engineering Team, driving the development of cutting-edge Xeon products tailored for cloud and datacenter markets. Your main focus will be on designing, developing, and implementing innovative Digital IO Controllers like PCIe, CXL, and UCIe systems for the next generation of data center and AI chips. With your unique blend of architectural know-how and hands-on RTL coding prowess, you'll bring ground-breaking designs to life. Collaborating closely with cross-functional teams, you’ll architect scalable memory coherency protocols, craft critical components of the memory fabric microarchitecture, and ensure optimal performance in RTL code. Your role will also involve mentoring junior engineers, staying ahead of emerging technologies, and analyzing system performance to optimize architecture for target use cases. If you possess a remarkable understanding of high-speed IO architectures and have a passion for innovation, this may be the perfect role for you at Intel where creativity meets cutting-edge technology!

Frequently Asked Questions (FAQs) for IP Micro Architect / RTL Logic Design Lead Role at Intel

What are the main responsibilities of the IP Micro Architect / RTL Logic Design Lead at Intel?

The IP Micro Architect / RTL Logic Design Lead at Intel is responsible for designing and implementing advanced Digital IO Controllers, such as PCIe, CXL, and UCIe systems, specifically targeted for data center and AI chips. This includes architecting scalable memory coherency protocols, developing RTL code for optimal performance, collaborating with cross-functional teams, mentoring junior engineers, and staying abreast of the latest trends and technologies.