ASIC Design & Integration Engineer

Come join Apple’s growing wireless silicon development team. Our wireless SOC organization is responsible for all aspects of wireless silicon development. With a particular emphasis on highly energy-efficient design and new technologies that transform the user experience at the product level, all of which is driven by a best-in-class vertically integrated engineering team spanning RF/Analog architecture, and design, Systems/PHY/MAC architecture, and design, VLSI/RTL design and integration, Emulation, Design Verification, Test and Validation, and FW/SW engineering. We encourage you to apply if you enjoy a fast-paced and challenging environment, collaborating with people across different functional areas, and growing during crisis times.

Description

As a Radio Integration Engineer, you will work in a team developing Wireless SoCs with custom hardware accelerators, as well as multiple ARM-based sub-systems. You will integrate industry standard and custom hardware IP into SoCs. You will work closely with SoC architects, IP developers to develop SoCs that meet the power, performance, and area goals for Apple devices. You will help define the processes, methods, and tools for the design and implementation of large complex SoCs. You will develop and maintain methodology and flow checks for your design. Interact with our verification team to ensure appropriate validation and coverage goals are met. You'll ensure security assumptions for the chip are accurately implemented within the blocks. Collaboration with multi-disciplinary groups to make sure designs are delivered on time and with the highest quality by incorporating accurate checks at every stage of the design process. In this highly visible role, you will be at the center of the ASIC Integration effort collaborating with all fields, with a critical impact on getting functional products to millions of customers quickly. Work with platform architects, system groups, and RFIC designers to develop digital modules within the RFIC. Modules can include, but are not limited to, SPI, calibration engines, high-speed digital front-end blocks for Tx/Rx, digital filters, and digital control. Design digital blocks for digitally intensive RF circuits like ADPLL, digital transmitters, and receivers. Develop signal processing intensive design for wireless communication SoCs, including: Write specifications and Microarchitecture definition. IP integration, RTL logic design, and DV support. Run tools to ensure lint-free and CDC clean design. Synthesis, timing constraints, equivalence check, and DFT insertion. Work with algorithm and software team to ensure performance and power efficiency. Bus fabric, especially APB/AHB/AXI. Chip-to-chip interface, especially SPI, I2C, PCIe, and USB. Power management with multiple power domains.

Minimum Qualifications

BS and 3+ years of relevant industry experience.

Preferred Qualifications

This position requires detailed knowledge of the ASIC design flow, synthesis, static timing analysis, scripting, and netlist generation. Relevant design experience in SoC and/or radio/transceiver, PLL Controller. Experience with Digital Mixed Signal design. Extraordinary leadership skills and ability to encourage team members with an innate ability to see the bigger picture. Passion for owning and driving design schedules using well-defined metrics. Experience working in a high-energy multi-disciplined engineering environment, strong at multi-tasking, and real-time crisis management. Ability to understand and extract action plans from sophisticated technical discussions and translate into succinct messaging for multi-functional and executive status reporting. Excellent debugging skills and shown ability to drive resolution of critical problems.