Wireless SOC Design Verification Engineer

As part of our team, you will have the opportunity to verifying complex SOCs. Our team integrates multiple sophisticated IP level DV environments, craft highly reusable best-in-class UVM Testbenches, implement effective coverage driven and directed test cases, deploy new tools, and implement methodologies to improve quality of tape-out readiness. By collaborating with other product development groups across Apple, you can push the industry boundaries of what wireless systems can do and improve the product experience for our customers across the world! You will be able to learn all aspects of a large-scale SOC, different types of SOC architectures, many high speed layered protocols, methodologies on low power architecture, best-in-class DV methodology. You will gain knowledge on Wireless protocols, FW-HW interactions, complexities of multi-chip SOC debug architecture. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing state of the art Wireless SOCs! This position comes with responsibility for pre-silicon RTL verification of block and top level SOC, comfortable with all areas of SOC Design Verification engineering, with an ability to thrive in a dynamic multi-functional organization, debate ideas openly, and deliver on complex Wireless protocol chip requirements.

Description

Understand details of High Efficiency SOC Architecture, standard SOC peripherals such as PCIE, Power Management & Low-Power schemes, DMA, CPUs and multi-processor systems, DDR, PCIe, Memory Controller Subsystems, USB, PLL, power up, Secured Boot schemes. Deliver on Power Management designs using low-power methodologies and power up-down scenarios using UPF simulations. Build coverage driven verification plans from specifications, review and refine to achieve coverage targets. Architect UVM based highly reusable test benches and integrate complex multi-instance VIPs, sub-system test benches and test suites to SOC level. Achieve targeted coverage, work with design, architecture, SW, FW and external IP delivery teams to efficiently integrate and verify overall SOC design. Work closely with DV methodology architects to improve verification metrics.

Minimum Qualifications

BS and a minimum of 10 years relevant industry experience.

Preferred Qualifications

Dedicated/hands-on ASIC & SOC DV experience. Sophisticated knowledge of HVL methodology (UVM/OVM) with most recent experience in UVM. Experience with formal verification is a plus. Proven track record of working full ASIC cycle from concept to tape-out to bring-up, including test-planning, testbench implementation, test sequence creation and debugging and coverage closure. Experience taping out large SOC systems with embedded processor cores. Hands-on verification experience of PCIe, Bus Fabric, NOC, AHB, AXI, based bus architecture in UVM environment. In-depth knowledge and experience working with low power design, UPF integration, boot-up, power-cycling, HW/FW interaction verification. Low Power Verification experience is a plus. Should be a phenomenal teammate with excellent communication and problem-solving skills and the desire to seek diverse challenges.