Job details

Principal Mixed Signal Design Verification Engineer

Astera Labs is a global leader specializing in high-speed connectivity solutions for AI and cloud infrastructure, seeking a Principal Mixed Signal Design Verification Engineer with extensive experience in UVM, C/C++, and verification of SerDes silicon products for Server, Storage, and Networking sectors.

Skills

Expertise in System Verilog, UVM, and advanced verification methodologies.
Proficiency in C/C++ programming and its integration with hardware verification environments.
Experience with scripting languages such as Perl and Python for test automation.
Strong debugging skills in mixed signal and firmware environments.
Knowledge of PCIe, Ethernet, and UAL PHY layer verification is a plus.
Familiarity with FPGA-based verification and emulation techniques.

Responsibilities

Develop and execute verification test plans and sequences in UVM for mixed signal designs.
Integrate and utilize Matlab, Simulink, C/C++ in System Verilog environments using DPI/PLI.
Automate verification infrastructure using scripting tools such as Perl and Python.
Collaborate with RTL designers to debug verification failures and analyze coverage data.
Develop random constraints and assertions for transaction-based verification methodology.
Perform end-to-end mixed signal SerDes verification including channel modeling and compliance testing.
Verify firmware integration for control and configuration of SerDes and related components.

Education

Bachelor’s degree in Electrical Engineering required.
Master’s degree in Electrical Engineering preferred.

Benefits

Collaborative work environment fostering innovation.
Opportunity to work at a market-leading technology company.
Diversity and inclusion encouraged and supported.
Engagement with cutting-edge AI, cloud, and semiconductor technologies.

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UVM SystemVerilog C++ Matlab Simulink SerDes Verification PCIe Ethernet FPGA Firmware Mixed Signal DPI PLI Python Perl

Astera Labs Glassdoor Company Review

5.0

Astera Labs DE&I Review

4.8

CEO of Astera Labs

Jitendra Mohan

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Average salary estimate

$180000 / YEARLY (est.)

min

max

$140000K

$220000K

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Astera Labs

Our Values: Our team values are integral to who we are and how we operate as a company. Customer Focus: We are intensely focused on customers' needs. Deliver Results: We execute in order to consistently prove our promise; on time, according to s...

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FUNDING

Series B

DEPARTMENTS

Engineering

SENIORITY LEVEL REQUIREMENT

Senior Level

INDUSTRY

Computer Hardware Development

TEAM SIZE