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Sr. Digital Design Verification Engineer

Fabric believes hardware determines the boundaries of humanity's collective creativity and imagination. We are building hardware for the next generation of cryptography because we believe in creating a more trustworthy world with secure, private computation at its core. Just as encryption and decryption enabled the Internet as we know it, this new paradigm of cryptographic algorithms, such as zero knowledge proofs, have even broader potential to revolutionize how trust, privacy, and identity work in our society.   


About the job

We are currently looking for Design Verification Engineers to join our team of brilliant, passionate people helping to create this breakthrough technology. 


What you'll be doing...
  • Contribute to the architecture and methodology of our DV environment and team from scratch.  
  • Develop and execute verification plans and test-benches to validate the functionality of our products.  
  • Work on verification of processor architecture, PCIe/memory controllers, SoC, and Network on chip (NOC) structures  
  • Write and maintain directed and constrained random tests to ensure that the verification environment is up-to-date and effective.  
  • Work cross functionally to integrate the verification environment into the overall design flow.  
  • Own and develop formal and UVM verification methods to ensure the completeness and consistency of the design.  
  • Provide technical guidance to other team members with the latest verification best practices and techniques.  


Qualifications and experience requirements
  • BS, MS,  PhD in Electrical Engineering, Computer Science, or a related field.  
  • 8+ years of strong experience with design verification, including simulation and formal verification.  
  • GPU/CPU/RISC-V/PCIe/Memory controller DV experience, NOC experience a plus 
  • UVM testbench development from scratch, SystemC/C++ experience a plus
  • Python knowledge and scripting/automating DV flows
  • Good understanding of digital design, including RTL design, UVM, System Verilog and synthesis
  • Knowledge of cryptography and data protection is a plus.  
  • Excellent written and verbal communication skills, and the ability to work effectively in a team environment. 
  • Ability to work independently, under pressure and in a startup setting.


Why Fabric of Cryptography?

Our benefits are here to support you!

Competitive salary and benefits

Comprehensive medical / dental / vision, STD/LTD, AD+D and Life Insurance

Flexible vacation and company paid holidays


We’re remote friendly.

We believe that your value to the team can be provided at one of our offices or from the comfort of your home. Depending on your function, enjoy the flexibility of remote work and join our growing community of remote employees in the US and around the world.  


We’re vested.

You won’t just own your work here; you’ll have the potential to own equity in our company. We are competing in a hardware market that is projected to grow exponentially, which gives our company valuation room to grow at tremendous rates.


Fabric Cryptography is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate based on race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.

What You Should Know About Sr. Digital Design Verification Engineer, Fabric of Truth, Inc

At Fabric, we're on a mission to redefine the boundaries of creativity and imagination through hardware. As a Sr. Digital Design Verification Engineer, you'll play a critical role in shaping the future of cryptography and secure computation. Join our passionate team, dedicated to developing cutting-edge technology that enhances trust and privacy in our digital society. In this role, you'll dive into the architecture and methodology of our design verification environment, craft and execute comprehensive verification plans, and collaborate across functions to seamlessly integrate these efforts into our overall design workflow. Your expertise in areas like processor architecture, PCIe, and SoC will be invaluable as you write directed and constrained random tests that ensure top-notch product functionality. Additionally, you will guide your teammates on best practices while continuously developing formal and UVM verification techniques. Your contributions will have a direct impact on creating and maintaining a robust and dynamic verification environment. We believe that our people are our most valuable asset, and with benefits that support work-life balance and diverse work settings, including remote options, we nurture a workplace where everyone can thrive. Bring your 8+ years of experience in design verification and a passion for innovation to Fabric and help us build a more secure world, one line of code at a time.

Frequently Asked Questions (FAQs) for Sr. Digital Design Verification Engineer Role at Fabric of Truth, Inc
What are the responsibilities of a Sr. Digital Design Verification Engineer at Fabric?

As a Sr. Digital Design Verification Engineer at Fabric, you'll be tasked with designing and implementing verification plans that evaluate the functionality of our groundbreaking cryptographic hardware. Your responsibilities will include developing testbenches, integrating verification environments into our design flow, and guiding your team on the latest best practices in design verification, covering areas from processor architectures to network-on-chip structures.

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What qualifications do I need to become a Sr. Digital Design Verification Engineer at Fabric?

To be considered for the Sr. Digital Design Verification Engineer position at Fabric, you should have a BS, MS, or PhD in Electrical Engineering or Computer Science, along with a minimum of 8 years of hands-on experience. Expertise in design verification methodologies, experience with UVM testbenches, and a solid understanding of digital design principles such as RTL design are essential. Additionally, knowledge of cryptographic principles is a strong plus.

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What is the work environment like for a Sr. Digital Design Verification Engineer at Fabric?

Fabric prides itself on fostering a flexible and inclusive work environment for all employees, including Sr. Digital Design Verification Engineers. The position offers remote work options, allowing you to balance your professional and personal life. You will collaborate with a diverse team dedicated to innovation, all while being given the freedom to work independently.

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What skills are essential for a successful Sr. Digital Design Verification Engineer at Fabric?

A successful Sr. Digital Design Verification Engineer at Fabric should possess strong analytical and programming skills, particularly in System Verilog and Python. Familiarity with UVM and modern validation techniques will aid in developing the verification environment. Furthermore, good interpersonal and communication abilities are necessary to thrive in a team-oriented atmosphere.

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How can being a Sr. Digital Design Verification Engineer at Fabric contribute to my career?

Working as a Sr. Digital Design Verification Engineer at Fabric allows you to play a key role in innovative technology development while enhancing your expertise in design verification. With opportunities to work with advanced cryptographic applications and a chance to potentially own company equity, you'll not only broaden your skill set but also participate in the growth of a company that is poised to lead in the hardware market.

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Common Interview Questions for Sr. Digital Design Verification Engineer
Can you explain your experience with UVM testbench development?

Certainly! In my previous roles, I've developed UVM testbenches from scratch, focusing on building efficient and maintainable verification environments. I always ensure that my testbenches are modular and scalable, which facilitates the introduction of new test cases and verification strategies. I would love the opportunity to share specific examples of projects I've worked on.

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What are the challenges you face when verifying complex digital designs?

One significant challenge in verifying complex digital designs is ensuring comprehensive coverage of all possible functional scenarios. To address this, I always implement a combination of constrained random testing and directed testing to improve coverage. Additionally, regular communication with design teams helps mitigate discrepancies early in the process.

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How do you stay current with the latest verification methodologies?

Staying current in the fast-evolving field of design verification is crucial. I regularly attend workshops, webinars, and conferences related to design verification technologies, and I'm an active member of several professional organizations where I can network with peers and share knowledge. Continuing education and online courses also play a vital role in my professional development.

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What tools do you prefer for simulation and verification?

I have experience using industry-standard simulation tools like ModelSim and QuestaSim, as well as verification tools like Synopsys VCS and Cadence Incisive. Depending on the project requirements, I choose the tool that best aligns with ensuring the performance and efficiency of the design under verification.

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Describe your approach to writing directed tests.

When writing directed tests, I base them on specific functional scenarios and requirements outlined in the specification documents. My approach includes developing a clear understanding of the expected outputs and corner cases while ensuring that each test minimizes ambiguity. I also add thorough comments for maintainability so that team members can easily understand complex test scenarios.

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Can you provide an example of a challenging verification issue you encountered and how you resolved it?

In a previous project, we faced a timing issue that caused intermittent failures. After extensive debugging, I created a detailed timing analysis to pinpoint the exact conditions leading to the failures. By collaborating closely with the design team to make adjustments and verify timing constraints, we successfully resolved the issue and improved design stability.

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What role does Python play in your verification workflows?

Python has been instrumental in automating various aspects of my verification workflows. From script generation for test cases to handling log files and custom reports, Python has improved efficiency dramatically. Additionally, using Python for pre-silicon validation tasks helps to enhance collaboration among verification engineers and streamlines our processes.

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How do you ensure that your verification environment aligns with overall design flow?

To ensure my verification environment aligns with the overall design flow, I regularly engage in cross-functional meetings with design engineers. This collaboration ensures that my verification methodologies and environments are incrementally updated to reflect any changes in the design process, ultimately streamlining the workflow and improving overall productivity.

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What methodologies do you use to validate processor architectures?

When validating processor architectures, I employ a combination of simulation, formal verification, and emulation methodologies. I develop comprehensive test plans that cover performance characteristics, corner cases, and security functions. Additionally, I leverage constraints and randomized testing to ensure thorough validation and catch edge cases early in the design cycle.

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How do you manage your time and priorities while working on multiple projects?

Managing time effectively involves setting clear priorities based on project deadlines, complexity, and team dependencies. I utilize task management tools to keep track of projects and their requirements while breaking tasks into actionable steps to ensure no detail is overlooked. Regular check-ins with the team also allow for updates and realignment on project goals.

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DATE POSTED
January 17, 2025

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