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DTCO APR Engineer

Job Details:

Job Description: 

Join Intel and seize the opportunity to innovate and expand computing technology, connecting and enriching the lives of every person on Earth. As a DTCO (Design Technology Co-Optimization) engineer, you will engage in all aspects of the SoC design flow, from high-level design to synthesis, place and route, timing, and power, to create optimal designs.

As a DTCO APR engineer, your responsibilities will include, but are not limited to:

  • Supporting RTL synthesis and conducting place and route experiments using both internal and external vendor tools to enhance Intel's product Power, Performance, and Area (PPA) for current and future process nodes on internal Intel Architecture (IA/X86) and external ARM IPs.
  • Managing changes in floorplan, corresponding scaling, and assessing their impact on power, congestion, and timing for the current technology node, while predicting their effects on power, routing, and timing scaling for the next technology node.
  • Improving cell utilization and transistor density metrics by leveraging cutting-edge tools and methodologies.
  • Analyzing power (dynamic and leakage), performance (setup and hold), enhancing critical path timing, reducing congestion by optimizing the use of available metal layers, debugging tools, and more.

Qualifications:

  • Bachelor's Degree (Master's Degree preferred) in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
  • 5+ years of relevant experience in silicon design and/or TFM development.


Experience in the following areas:

  • Proficiency in at least one of the following: Python, Perl, TCL, Shell scripting.
  • Use of industry-standard placement and routing CAD tools.
  • Proven track record in Si Tape Out.


Preferred Qualifications:

  • Experience in floor planning and power grid setup, clock methodologies, IR droop and SI mitigation strategies, power and timing signoff conditions, and leveraging industry-standard tools, flows, and methodologies to achieve optimal PPA tradeoffs.
  • Experience in feasibility studies or technology pathfinding.
  • Experience in more than one ASIC Digital Implementation TFM ( SNPS / CDNS / Others ).
  • Background in Artificial Intelligence and Machine Learning (AI-ML).


#DesignEnablement #DesignTechnologyPlatform

          

Job Type:

Experienced Hire

Shift:

Shift 1 (Malaysia)

Primary Location: 

Malaysia, Penang

Additional Locations:

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$100000 / YEARLY (est.)
min
max
$80000K
$120000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About DTCO APR Engineer, Intel

Join Intel as a DTCO APR Engineer in beautiful Penang, Malaysia, and dive into the world of innovative computing technology! In this role, you'll be at the forefront of System on Chip (SoC) design, gaining hands-on experience from high-level design all the way to synthesis, place and route, timing, and power optimizations. Your key responsibilities will revolve around supporting RTL synthesis and conducting experiments using top-tier internal and external vendor tools, focusing on enhancing performance, power, and area (PPA) for both Intel's architecture and ARM IPs. You’ll manage floorplan changes and analyze their impact on power and timing while pushing the envelope to improve cell utilization and density metrics through cutting-edge methodologies. Plus, you’ll get to leverage your scripting skills in Python, Perl, or TCL to implement significant design improvements. With a Bachelor's or Master's in Electrical or Computer Engineering and over five years of silicon design experience, you’ll find this position dynamic and rewarding. Here at Intel, we are not just about chips; we are about making a difference in the lives of people worldwide. If you’re ready for the next step in your career and want to collaborate with brilliant minds in a hybrid work environment, this is the perfect opportunity for you!

Frequently Asked Questions (FAQs) for DTCO APR Engineer Role at Intel
What are the key responsibilities of a DTCO APR Engineer at Intel?

The DTCO APR Engineer at Intel focuses on all aspects of the SoC design flow, including RTL synthesis, place and route experiments, and optimizing Power, Performance, and Area (PPA) using high-level design methodologies. They also manage floorplan changes, analyze power and timing, and improve cell utilization using cutting-edge tools.

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What qualifications do you need to become a DTCO APR Engineer at Intel?

To qualify for the DTCO APR Engineer position at Intel, candidates ideally possess a Bachelor’s or Master’s Degree in Electrical Engineering or a related field, along with over five years of relevant experience in silicon design. Proficiency in scripting languages and familiarity with CAD tools is essential.

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What skills are essential for a DTCO APR Engineer working at Intel?

Essential skills for a DTCO APR Engineer at Intel include proficiency in scripting languages like Python or Perl, expertise with CAD tools for placement and routing, and a solid understanding of power analysis and timing signoff conditions. Experience with ASIC Digital Implementation is also beneficial.

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What kind of projects does a DTCO APR Engineer at Intel work on?

As a DTCO APR Engineer, you'll work on a variety of projects involving the optimization of SoC designs. This includes troubleshooting and improving existing designs while also experimenting with new technologies to enhance PPA metrics using innovative methodologies.

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What is the work model for a DTCO APR Engineer at Intel in Malaysia?

The DTCO APR Engineer position at Intel in Penang, Malaysia, follows a hybrid work model, allowing employees to balance time effectively between working on-site and remotely, offering flexibility in how you manage your work environment.

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Common Interview Questions for DTCO APR Engineer
What is your experience with RTL synthesis?

In answering this question, detail specific projects where you utilized RTL synthesis. Highlight your role, the tools you used, and the outcomes achieved, especially regarding improving design efficiency or performance metrics.

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How do you approach floorplanning in SoC design?

Discuss your methods for analyzing design requirements and how you manage area, power, and timing constraints. Provide examples of how you’ve tackled challenges in floorplanning and the strategies that worked best.

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Describe your experience with power analysis techniques.

Explain the various power analysis techniques you've employed, such as dynamic and leakage power analysis. Provide examples of the impact your analyses had on design decisions and overall efficiency.

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What CAD tools are you familiar with for place and route processes?

List the CAD tools you have experience with, such as Synopsys or Cadence, and explain your proficiency level. Mention how you’ve used these tools to solve routing congestion issues or enhance design outcomes.

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How do you ensure optimal PPA tradeoffs in your designs?

Discuss your methodology for evaluating tradeoffs between power, performance, and area. Provide specific examples of projects where you've successfully balanced these elements to achieve optimal results.

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Can you explain a challenging issue you faced during a previous project?

Share a project-related challenge, your approach to resolving it, and the eventual outcome. Highlight the problem-solving skills or tools that were key to overcoming the obstacle.

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What scripting languages do you use and how do they enhance your work?

Identify the scripting languages you are proficient in, such as Python or Perl, and explain specific projects where scripting helped automate tasks or improve workflow efficiency in your design processes.

Join Rise to see the full answer
How do you stay updated with the latest trends in design technology?

Talk about your methods for continuous learning, whether through online courses, industry conferences, or peer collaboration. Mention specific trends or technologies you’re currently exploring or implementing.

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What role does teamwork play in your approach to design engineering?

Emphasize the importance of collaboration in engineering projects. Provide examples of how teamwork has led to improved outcomes in your previous experiences and how you contribute to an effective team dynamic.

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How do you handle tight deadlines in design projects?

Describe your time management strategies, prioritization skills, and how you ensure quality work under pressure. Include examples from past experiences where you successfully met or exceeded deadlines.

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BADGES
Badge ChangemakerBadge Diversity ChampionBadge Flexible CultureBadge Global CitizenBadge Work&Life Balance
CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
April 17, 2025

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