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Mixed Signal Logic Design Engineer - job 2 of 2

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Job Details:

Job Description:

The Client DDRPHY team is looking for an energetic and passionate Logic Design Engineer who will work on high-speed digital design targeted towards low power optimized IP implementations. Your responsibilities will include, but are not limited to - defining microarchitecture features of the block being designed, implementing RTL in System Verilog, setting up Automation flows for IP Logic Design, ensuring RTL quality via Front End tools like Lint, CDC, VCLP, Synthesis QA checks etc, creating innovative automated solutions to help Logic Design in areas like Coverage closure, timing convergence etc. The selected candidate will be part of a growing, dynamic team, interacting with many cross functional teams and working in an innovative environment.

Objectives of the position

Own and deliver the logic design of Mixed Signal IPs.
Continuously drive turnaround time improvements, robustness of Logic design via Architecture engagement and Tools/Methodology improvements.
Drive area/power efficiency of IPs and come up with improvements on IP Area/Power metrics.
Critical Decision making on technical issues.

Qualifications:

The candidate should possess a BS, MS degree with 6+ years of relevant industry experience. Candidate should have worked on IP or SoC RTL logic development using Verilog/System Verilog.

Experience in the following areas/skills are desired:

Logic design using System Verilog
Low-power design using UPF and clock gating
Multiple clock domain design
State machine design
Simulation and debug experience using VCS/Verdi
Synthesis and speed path debug
Git/Perforce/CVS know how
Strong Perl/Python/TCL scripting skills
Front-End Design tools like Spyglass or VC Lint, CDC, DFT, VCLP
Excellent written and verbal communication skills
DDR PHY and/or Memory Controller Design domain knowledge is a plus
Experience with DFI/DDR/LPDDR Protocols is a plus
Basic understanding of analog design to drive an optimal solution between analog and digital designs is a plus
Familiarity with pre-silicon and post-silicon validation is a plus

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location:

India, Bangalore

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$75000 / YEARLY (est.)

min

max

$60000K

$90000K

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What You Should Know About Mixed Signal Logic Design Engineer, Intel

Are you ready to take your career to the next level? Join the dynamic DDRPHY team at our company as a Mixed Signal Logic Design Engineer in Bangalore, India! We're on the lookout for a passionate and energetic individual who thrives in high-speed digital design environments, especially in low-power optimized IP implementations. In this role, you will define the microarchitecture features of the blocks you design and implement RTL in System Verilog. You'll be crucial in setting up automation flows for IP Logic Design and ensuring RTL quality through various front-end tools like Lint, CDC, and synthesis QA checks. We value innovation, and your creative solutions for challenges like coverage closure and timing convergence will make a difference! As a member of our team, you'll collaborate across multiple functions and drive key initiatives aimed at improving turnaround times and efficiency. So, if you have a BS or MS degree with 6+ years in the industry, and skills in areas such as logic design, low-power design techniques, simulation, and scripting, we want to hear from you! Not only will you contribute to exciting projects, but you'll also be part of a company that values the potential in people and strives to deliver purposeful computing experiences. Together, let's unlock possibilities and enrich lives globally!

Frequently Asked Questions (FAQs) for Mixed Signal Logic Design Engineer Role at Intel

What are the main responsibilities of a Mixed Signal Logic Design Engineer at the company?

As a Mixed Signal Logic Design Engineer, your primary responsibilities will include defining microarchitecture features, implementing RTL in System Verilog, setting up automation flows, and ensuring the quality of RTL via front-end tools like Lint and CDC. You'll also focus on driving improvements in turnaround time and logic design robustness.