Mixed Signal Systems Design Engineer

Based in Southern California with locations in Malibu, Calabasas, Westlake Village and Camarillo; HRL has been on the leading edge of technology, conducting pioneering research and advancing the state of the art. 

This position will lead the Systems Engineering activities for research and development efforts from system conceptual design, concept, requirements development, architecture definition, and design definition of various demonstrations to establish technology readiness and identify long lead development needs, this position is a system engineering role, but requires significant prior design experience in ASIC (Analog & Digital design. The ideal candidate will have completed several full product lifecycles starting with basic concepts and moving through architecture definition, trades, requirements development, design, implementation, manufacturing, and verification.   The ideal candidate will have a skill mix of about 30% system engineering experience and about 70% design & implementation experience. This position requires working with mathematicians, physicists, and other researcher scientists to migrate concepts into well-defined architectures and requirements.  The ideal candidate will have a natural intellectual curiosity that drives them to learn and understand new frontiers in physics, math, materials science, and software. This position regularly tackles problems that are beyond start of the art.  Hence this position requires experience navigating nebulous needs, iterative architectures, and a low TRL environment.

Essential Duties:

Lead systems engineering efforts in maturing technologies under development and defining requirements and capabilities in an agile model-based engineering environment.

Lead the content development and execution of Preliminary and Critical design reviews for a collection of HW, SW, and Firmware designs to be used in experiments.

Partner with researchers and technology experts in understanding technology development current state and future goals to inform test, verification, and validation efforts

Lead system engineering task execution for development of Systems Electronics/Device Modeling and integration with larger system(s).  Integrate technologies under development with larger system concept of operations and determine impacts to interfaces, integration techniques, manufacturability, and integrated system testing.

Define functional architecture and modeling needs and integrate efforts with functional architecture and modeling/simulation teams to meet end item deliverable test, verification & validation dates

Work with design teams to optimize control, timing, data flow, power distribution, signal integrity, power cleanliness, etc. in ASICs to achieve highly constrained analog outputs

Work with Scientists to understand the needs of experiments and codify key functionality in functional block diagrams that partition functionality across different platforms (ASICs, FPGA’s, GPU’s, CPU’s) based on meeting key technical parameters such as noise, latency, bit error rates, thermal dissipation.

Work with Scientists to understand the needs of experiments and codify key requirements for hardware, software, and firmware for a mixture of products such as ASIC’s, FPGA’s, Printed Circuit Boards inclusive of functional requirements, performance requirements, interface requirements, environmental requirements.

Work with Scientists to understand the needs of experiments and codify in detailed system interconnect diagrams that capture all the HW along with the signals and data flowing between HW, SW, and Firmware.  This information is used to then write detailed interface requirements that define the electrical, mechanical, and data requirements.

Work with scientists to understand the needs of experiments and codify in custom functional blocks or COTS IP in ASIC devices.

Required Skills:

A skill mix of about 30% system engineering experience and about 70% design & implementation experience.

Significant (15+ years) prior experience in ASIC (analog & digital), FPGA, and firmware design, implementation, & verification.

9+ years of experience in system design, analysis, modeling, simulation, verification, and validation

Minimum of one full ASIC lifecycle from concept through circuit design, layout, place & route, verification, and tape-out. 

Experience with power distribution network design that minimizes and mitigates sources of noise,

Some experience with optimization of noise and power for analog portions of the ASIC.

Experience communicating with verbal and written communication skills, with ability to work with both technical and non-technical stakeholders

Experience in a Lead Engineer role responsible for ensuring system, product/capability development, and product integration across multiple disciplines

Demonstrated leadership for driving technical problems and issues to closure

Preferred experience with mixed signal and or analog design.

To execute these tasks the candidate should have several iterations of experience with the full lifecycle of a mixed signal ASIC.   Ideal candidates will also have lifecycle experience with multilayer printed circuit board design.

Required Education:

Bachelor's, Master’s, or Doctor of Science degree from an accredited course of study, in engineering, computer science, mathematics, physics, or chemistry

Special Requirements:

This position requires a current Tier 5 (T5), formerly known as a Single Scope Background Investigation (SSBI) (U.S. Citizenship required) or requires candidate agreed to enter a Continuous Evaluation program.

Compensation:

The base salary range for this full-time position is $182,720 - $234,168 + bonus + benefits.  

Our salary ranges are determined by role, level, and location. The range displayed on each job posting reflects the target for new hire salaries for the position. Individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specifics during the hiring process. Please note that the compensation details listed reflect the base salary only, and do not include potential bonus or benefits.

Don’t meet every single requirement? Studies have shown that some people are less likely to apply to jobs unless they meet every single desired qualification. At HRL, we are dedicated to building a diverse, inclusive, and authentic workplace, so if you’re excited about this role but your past experience doesn’t align perfectly with every qualification in the job description, we encourage you to apply anyway. You may be just the right candidate for this or other roles.

HRL offers a generous and very competitive total compensation and benefits package. Our Regular/Full Time benefits include medical, dental, vision, life insurance, 401K match, gym facilities, PTO, growth potential, and an exciting and challenging work environment (https://www.hrl.com/careers/benefits).

HRL Laboratories is an Equal Employment Opportunity employer and does not discriminate in recruiting, hiring, training or promoting, on the basis of race, ethnicity, color, creed, religion, sex, sexual orientation, gender, gender identity, genetic information, national origin, physical or mental disability, pregnancy, medical condition, age, U.S. military or protected veteran status, union membership, or political affiliation. We maintain a drug-free workplace and perform pre-employment substance abuse testing.

For our privacy policy please visit : www.hrl.com/privacy

This position must meet Export Control compliance requirements, therefore a "U.S. Person" as defined by 22 C.F.R. § 120.15 is required. "U.S. Person" includes U.S. Citizen, lawful permanent resident, refugee, or asylee.