Job details

Principal Post-Silicon - DDR, Validation Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Support customer silicon bringups and post silicon queries of our IP and help to debug customer issues with same. Debug issues with customer chips and boards as needed when they are unable to reproduce Cadence test chip results.

Position Requirements

Candidate’s background should include a minimum 4 years of silicon validation experience, in the area of DDR
Good understanding of lab equipment and measurement techniques for high speed interfaces. High speed scopes, probes, spectrum analyzers, BERTs.
Knowledge of DDR trainings and memory system operation a must
Software proficiency for test scripting, data handling and reporting using scripting languages such as Python, TCL etc.
Programming skill in C/C++/C# is desirable
Able to run Verilog test benches and view waves to debug issues
Communicate with global teams (US, India, China, EU), which work in different time-zones
Excellent problem-solving skills, good communication skills and ability to work cooperatively in a team environment
Work with design team to understand requirements, fashion tests and review results
BEng, MEng

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The annual salary range for California is $128,100 to $237,900. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

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