- Static timing analysis and timing closure (TOP and block).
- Propose technical solution to enhance the design from RTL to GDS to achieve timing closure.
- Collaborate with FE/BE teams to finish chip design within definited schedule.
- Bachelor or Master Degree in Information Technology/Computer
- Engineering/Computer Science/Telecoms/Electronics or similar.
- Experienced in Timing closure & tape out projects.
- Understanding of PnR design, CTS design & Sign-off.
- Have knowledge in logic related design activitíe (clock design, system control design, synthesis, RTL design, DFT design,...) is a plus point.
- Solid knowledge in using EDA tool (Synopsys, Cadence,...)
- Good written and oral communication (in English) & interpersonal skills
- Strong team-oriented working and good relationship-building with others
Renesas is an embedded semiconductor solution provider driven by its Purpose ‘To Make Our Lives Easier.’ As the industry’s leading expert in embedded processing with unmatched quality and system-level know-how, we have evolved to provide scalable and comprehensive semiconductor solutions for automotive, industrial, infrastructure, and IoT industries based on the broadest product portfolio, including High Performance Computing, Embedded Processing, Analog & Connectivity, and Power.
With a diverse team of over 21,000 professionals in more than 30 countries, we continue to expand our boundaries to offer enhanced user experiences through digitalization and usher into a new era of innovation. We design and develop sustainable, power-efficient solutions today that help people and communities thrive tomorrow, ‘To Make Our Lives Easier.’
At Renesas, you can:
Are you ready to own your success and make your mark?
Join Renesas. Let’s Shape the Future together.
Renesas Electronics is an equal opportunity and affirmative action employer, committed to supporting diversity and fostering a work environment free of discrimination on the basis of sex, race, religion, national origin, gender, gender identity, gender expression, age, sexual orientation, military status, veteran status, or any other basis protected by law. For more information, please read our Diversity & Inclusion Statement.
If you’re an experienced Sr STA Engineer, Renesas in Ho Chi Minh, Vietnam, has an exciting opportunity waiting just for you! In this dynamic role, you'll dive into static timing analysis and timing closure, taking charge of both top-level and block-level designs. Your expertise will be crucial as you propose technical solutions to enhance our designs from RTL to GDS, ultimately achieving timing closure. Collaboration is key here, so you’ll be working closely with our front-end and back-end teams to ensure timely chip design completion. With a solid background in Timing closure and tape-out projects and a profound understanding of PnR design and CTS design, you’ll be well-equipped to make a significant impact. We’re looking for candidates with strong foundations in EDA tools such as Synopsys and Cadence, as well as excellent written and oral communication skills. At Renesas, we’re not just about technology; we value a supportive and inclusive work environment where every team member can thrive. Join us to shape technology that makes lives easier and be part of a community dedicated to innovation and excellence.
Renesas Electronics Corporation delivers trusted embedded design innovation with complete semiconductor solutions. Renesas provides quality and comprehensive solutions for a broad range of Automotive, Industrial, Home Electronics (HE), Office Auto...
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