RTL and Firmware Design Coop/Intern (Power Management, Design-For-Debug)

As a Co-op/Intern you can get hands-on experience and make an immediate contribution to AMD's next generation of technology innovations. You will have unique opportunities to develop your career, connect with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more

RTL and Firmware Design Coop/Intern (Power Management, Design-For-Debug)

LOCATION:
Santa Clara, CA.

WHAT KIND OF ROLE IS THIS:
Onsite: This is an onsite position – the intern/co-op is required to relocate and work full-time (40 hours) from the location office.

PROGRAM TERM:
Fall: Start Date August 21, 2023 - December 15, 2023

WHAT YOU’LL BE DOING:

You will be working with a very experienced team of processor architects and RTL designers developing Power Management and Design-For-Debug microarchitecture and RTL of a next generation microprocessor. A successful candidate will have relevant course and project work in Processor Architecture, Digital Logic Design and RTL Coding with Verilog or VHDL. Responsibilities can extend to related Firmware or Design Description Language assignments for candidates who are interested.

KEY QUALIFICATIONS:

• Senior year MS candidate in CS/CompE/ECE/EE with in-depth knowledge of Processor Design
• Digital Logic design & RTL coding; preferably using Verilog, for a complex processor block
• Experience with Firmware or a Design Description Language is a plus.
• Ideally have good exposure to Physical Design and Verification methods.

• Compensation range from $32.00-$50.00 hourly commensurate with experience.