SOC Design Engineer, STAFF

At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design. If you share our passion for innovation, we want to meet you.Our System Solutions business is about integrating more capabilities into an SoC (System on Chip) —faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. We offer world-class Synopsys EDA tools for SOC design, development, and physical implementation through quality sign-off processes to ensure first-time right silicon. Within our System Solutions Group organization, we provide Design Services from specification to GDSII for all areas of SoC development. We help our customers design, verify, integrate more capabilities, and do the SOC physical implementation meeting the unique performance, power, and die size requirements of their target application.For this role, the focus will be working on Aerospace and Government customer SOC programs. The SOC Physical Design Engineer will have responsibilities for all aspects of doing physical design implementation from RTL to GDSII. This can include augmentation being an extension of our customer team with key responsibilities that can include working SOC top-level, block-level/sub chip-level for all areas of physical design implementation and design closure. This role can include incremental methodology development, flow development, and contribute towards improvements across development teams within Synopsys and with our customer environments delivering to World Class standards.The SOC Physical Design Engineer should have a strong background and experience and a proven track record. The candidate must be able work well within a team environment ensuring completion of their his/her responsibilities and the success of the SOC Physical Design implementation by delivering to high-quality standards. The individual is able adapt, recognize, and mitigate risks, and work proactively with contingency plans through the SOC development process to ensure all goals and objectives met.SOC Physical Design Engineer, StaffPosition Requirements:• BS or MS with 5yrs+ experience• Experience with Synopsys DC, DCG, DC TOPO a plus• Experience with Synopsys Fusion Compiler/ICC2 (Synthesis, DFT insertion, Place & Route, Chip Finishing, PT-SI STA, Timing Closure, PV (DRC/LVS/ERC/PERC)• Experience with Synopsys Flow Development & SOC implementation methodologies that will be deployed and used by our Synopsys customer’s Physical Design Implementation team members• Familiar with Synopsys Lynx a plus• RTL Hand-over experience a plus for RTL to GDS• Experience with top-level floor-planning, bump-maps, RDL IO Pad/Ring creation/verification, power grid creation/verification, hierarchal floor-planning/partitioning a plus• Solid experience with full SOC clocking methodologies (H-Tree, Structure Clocking, MS CTS for Top/Blocks with push/down & bottoms up approaches) a plus• Proficient with SDC STA constraints development driving back-end physical design tools for blocks and full-chip through timing closure & sign-off a plus• Ability to define sign-off requirements/margins based on Foundry technology requirements a plus• Understanding DFT structures such as JTAG, scan/TDF compression, and MEMBIST a plus• Synopsys Formality for formal verification (RTL to Gate, Gate-to-Gate) & Formality ECO flows or other 3rd party tools a plus• Familiar with UPF flows & methodologies for multi-voltage power domains with turn on/turn off using UPF a plus• Synopsys ICV for PV (Physical Verification – DRC/ERC/LVS/PERC) or 3rd party a plus• Ansys Redhawk SC (For IR analysis for static & dynamic EMIR) a plus• Experience in PD implementation/design closure on complex IP Sub-Systems such as PCIe, USB, MIPI, DDR, & HBM a plus• Experience with GlobalFoundries, TSMC, & Samsung technology nodes is a plus• Solid track record on execution delivering to high-quality standards for delivering to high-quality tape-out• Demonstrated ability to work independently and in cross-functional teams• This position may include assignment to government contracts. Consequently, the ability to obtain government security clearances and/or other work clearances is preferred and will be required in the event of assignment to government contract work.• Candidate having ASIC design center technical SOC physical design implementation, design closure experience and having customer interfacing experience a plusThe SOC Physical Design Engineer needs to work well with cross-functional team members both within Synopsys and with our customer base to meet their SOC development objectives. If you have the experience and are passionate and energetic with what is described to continue to grow and develop in all areas working in a World Class organization within Synopsys, please apply.The Salary Range for this position is $114000-$172000