Job details
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Staff CPU RTL Engineer, Shared Cache
Tenstorrent is seeking an experienced Cache RTL design engineer to join their innovative team, focusing on high-performance RISC-V CPU development and cutting-edge AI technology.
Skills
- Cache microarchitecture knowledge
- Logic design expertise
- Experience with hardware description languages
- Strong problem-solving abilities
- Calibration of performance and power evaluations
Responsibilities
- RTL coding in Verilog utilizing industry tools and open-source infrastructure
- Microarchitecture and design of processor L2 and LLC for high-performance computing
- Drive design trade-offs in collaboration with performance and physical design engineers
- Improve power, performance, and area of design through innovative techniques
- Debug RTL/logic issues in pre-silicon and post-silicon environments
Education
- BS/MS/PhD in Electrical Engineering or related field
Benefits
- Highly competitive compensation package
- Equal opportunity employer
To read the complete job description, please click on the ‘Apply’ button
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FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
No info
LOCATION
SALARY RANGE
$100,000/yr - $500,000/yr
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
November 5, 2024
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