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Analog Design Engineer - job 2 of 2

Job Details:

Job Description: 

IPG/HSIO is chartered to provide high speed serial link IPs to various internal and external SoCs within the Intel eco-system. Key IPs that we work on include PCI Gen6 and 80 Gbps Type-C USB PHYs.

Analog Design Engineer is responsible for analog circuit Design and corresponding Sign-off Verification (Functional, reliability, Mixed-Signal Verification etc) for custom circuits like CTLE, DCO, DFE, Tx and high speed clocking along with leading teams of junior engineers, driving the closure of macro-blocks and IPs and mentoring junior engineers.

What we are looking for is strong hands-on technical skill in high speed mixed-signal circuit design, initiative, ability to think in terms of the overall system and take the decisions necessary to build a better solution for Intel, ability to work in teams, ability to handle pressure and communicate both up and down the chain effectively.

Objectives of the position

  • Own and deliver the Circuit Design/Sign-off verification of high-speed serial link building blocks.
  • Drive Post-silicon electrical validation, post silicon debug and high-volume manufacturing support for the IPs.
  • Groom the junior team members towards technical excellence, drive innovation in the team and harvest publications/patents.
  • Work with internal stakeholders such as post-silicon validation teams, mask design for circuit implementation and logic design to design the analog/digital interface
  • Continuously drive the Turnaround time, robustness of circuit design and area/power of IPs.

Desired Competencies and Experiences:

  • Experience in working with cutting edge silicon technologies.
  • Deep understanding of Circuit design/ physical design of Analog Designs on advanced process technologies.
  • Expertise on high speed serial link design. Hands-on experience in blocks like Continuous Time Linear Equalizer (CTLE), Digitally Controlled Oscillator (DCO), Decision Feedback Equalizer (DFE), NRZ/PAM-3/4 Transmitter and high speed clocking.
  • Expertise in working with post-silicon test engineers.
  • Expertise on Reliability aware design and familiarity with Aging and RV tools. Ability to design floor plan and routing in Layout.
  • Good grasp on Industry standard tools such as Cadence design Environment (ADEXL or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools etc.
  • Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks
  • Strong communicator and proven leadership experience, self-driven, proactive nature to own and deliver high quality end to end Analog designs
  • Fast learner, good problem-solving skills, multitasking ability and attention to quality and detail.
  • Experience with MATLAB and serial link system analysis will be a major plus.

    Qualifications:

    Education:

    • BS/MS - EE/CS and 10+ Years of industry experience.

              

    Job Type:

    Experienced Hire

    Shift:

    Shift 1 (India)

    Primary Location: 

    India, Bangalore

    Additional Locations:

    India, Hyderabad

    Business group:

    IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

    Posting Statement:

    All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

    Position of Trust

    N/A

    Work Model for this Role

    This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

    Average salary estimate

    $125000 / YEARLY (est.)
    min
    max
    $100000K
    $150000K

    If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

    What You Should Know About Analog Design Engineer, Intel

    Are you an experienced Analog Design Engineer looking for a thrilling opportunity at Intel in Bangalore, India? Join our dynamic IPG/HSIO team, where we focus on designing high-speed serial link IPs, like PCI Gen6 and 80 Gbps Type-C USB PHYs. In this role, you’ll take the reins in analog circuit design and corresponding sign-off verification, working with custom circuits such as CTLE, DCO, DFE, and high-speed clocking. You will not only lead and mentor a team of junior engineers, but you will also be responsible for driving the innovative closure of macro-blocks and IPs. We're searching for someone with strong hands-on technical skills in high-speed mixed-signal circuit design, capable of communicating effectively with both your team and senior stakeholders. You’ll be tasked with electrical validation, post-silicon debugging, and support for high-volume manufacturing of our cutting-edge IPs. With your experience in advanced silicon technologies and expertise in high-speed serial link design, you'll play a crucial role in continually improving design turnaround time and the robustness of our circuits. This is more than just a job; it's a chance to shape the future, cultivate talent, and contribute to the transformation of Intel's silicon design process. If you thrive on challenge and innovation and possess a keen eye for detail and quality, this is the role for you!

    Frequently Asked Questions (FAQs) for Analog Design Engineer Role at Intel
    What are the main responsibilities of the Analog Design Engineer role at Intel?

    As an Analog Design Engineer at Intel, your main responsibilities include leading the analog circuit design and sign-off verification for high-speed serial link building blocks. You will manage teams of junior engineers, work on post-silicon electrical validation, and support high-volume manufacturing. Your expertise in mixed-signal circuit design will be essential in driving innovation within the team, as well as helping in mentoring junior members.

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    What qualifications are required for the Analog Design Engineer position at Intel?

    To qualify for the Analog Design Engineer position at Intel, you should possess a BS/MS in Electrical Engineering or Computer Science along with 10+ years of industry experience. You should have deep knowledge in circuit design, especially within advanced process technologies, and experience working with high-speed serial links. Expertise in tools like Cadence design environment and familiarity with post-silicon testing are also essential.

    Join Rise to see the full answer
    What skills are essential for success as an Analog Design Engineer at Intel?

    Success as an Analog Design Engineer at Intel hinges on technical expertise in high-speed mixed-signal circuit design, effective communication skills, and leadership ability. Proficiency in industry-standard tools, reliability-aware design, and a proactive approach to problem-solving are crucial. Familiarity with MATLAB and serial link system analysis can provide an additional edge.

    Join Rise to see the full answer
    How does team collaboration work for Analog Design Engineers at Intel?

    Team collaboration for Analog Design Engineers at Intel is vital for success. You will work closely with post-silicon validation teams, as well as design and logic engineers to create innovative solutions for circuit implementation. The role emphasizes the importance of communication and teamwork, as engineers collectively strive to ensure quality and innovation in analog design.

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    What is the work model for the Analog Design Engineer role at Intel?

    The Analog Design Engineer position at Intel adheres to a hybrid work model. This flexible arrangement allows you to split your time between working on-site and off-site. This work model fosters a balance between collaboration in person and the benefits of working remotely, giving you the best of both worlds.

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    Common Interview Questions for Analog Design Engineer
    Can you explain the importance of Mixed-Signal Verification in your role as an Analog Design Engineer?

    Mixed-Signal Verification is crucial as it ensures the functionality and reliability of the analog circuits you've designed. It helps to identify any inconsistencies or potential issues before the design reaches production. In your response, emphasize your understanding of the verification processes and how you've applied them in your past projects.

    Join Rise to see the full answer
    Describe your experience with high-speed serial link design procedures.

    In answering this question, focus on your previous work regarding high-speed serial links such as PCI Gen6 and USB PHYs. Discuss specific methodologies you used, challenges faced, and how you ensured reliability and performance in your designs, showcasing your hands-on experience.

    Join Rise to see the full answer
    How do you approach mentoring junior engineers in a team setting?

    Mentoring is about encouraging growth and knowledge sharing. Discuss how you identify the strengths and areas for improvement in junior engineers, provide constructive feedback, and create a supportive environment for learning, ensuring that you lead by example.

    Join Rise to see the full answer
    What tools do you typically use for circuit design and verification?

    In your response, mention industry-standard tools like Cadence design environment, ADEXL, or Virtuoso. Provide examples of how you've utilized them for circuit design, verification, and layout extraction in previous projects.

    Join Rise to see the full answer
    Can you share an example of how you improved the turnaround time of a circuit design project?

    Share a specific situation where you implemented changes that resulted in faster turnaround times, whether through process improvements, tool optimization, or team delegation. Highlight the impact this had on overall project timelines and goals.

    Join Rise to see the full answer
    What strategies do you use to handle the pressure of tight deadlines in your projects?

    In high-pressure situations, effective prioritization, time management, and effective communication are key. Discuss how you break down large tasks into manageable ones and keep your team informed to ensure everyone is aligned and moving towards the same deadline.

    Join Rise to see the full answer
    Describe a challenging analog design problem you encountered and how you resolved it.

    Relate a specific example of a complex design issue, detailing your thought process in analyzing the problem and the steps you took in collaboration with your team to find a solution. Highlight any innovative measures or techniques you employed.

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    How do you ensure quality in your circuit designs?

    Quality assurance starts from the design stage. Discuss your verification processes, methodologies, and use of reliability-aware design practices to ensure zero bugs and high performance in the final product.

    Join Rise to see the full answer
    What experience do you have with post-silicon validation?

    Post-silicon validation is critical for ensuring that designs work as intended after fabrication. Explain your hands-on experience with this process, including how you've collaborated with validation teams to troubleshoot issues encountered post-production.

    Join Rise to see the full answer
    How do you approach continuous learning in the field of analog design?

    Express your commitment to staying updated with industry advancements by participating in training, workshops, conferences, and reading recent publications. Mention how this knowledge has directly contributed to your work and innovation in projects.

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    MATCH
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    BADGES
    Badge ChangemakerBadge Diversity ChampionBadge Flexible CultureBadge Global CitizenBadge Work&Life Balance
    CULTURE VALUES
    Inclusive & Diverse
    Rise from Within
    Mission Driven
    Diversity of Opinions
    Work/Life Harmony
    Growth & Learning
    Transparent & Candid
    Customer-Centric
    BENEFITS & PERKS
    Snacks
    Onsite Gym
    Family Coverage (Insurance)
    Medical Insurance
    Dental Insurance
    Vision Insurance
    Mental Health Resources
    Life insurance
    Disability Insurance
    Health Savings Account (HSA)
    Flexible Spending Account (FSA)
    Learning & Development
    Paid Time-Off
    401K Matching
    Maternity Leave
    Paternity Leave
    FUNDING
    DEPARTMENTS
    SENIORITY LEVEL REQUIREMENT
    TEAM SIZE
    EMPLOYMENT TYPE
    Full-time, hybrid
    DATE POSTED
    April 11, 2025

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