Job details

Design Verification Engineer, Senior Staff

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution. Ready to come find your playground? Together, we can help shape the endless possibilities of AI.

Location:

Hybrid, working onsite at our Santa Clara, CA headquarters 3 days per week.

The role: Design Verification Engineer, Staff

What you will do:

We want to build a company and a culture that sustains the tests of time. We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally. We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey. We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge. The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business.

What you will bring:

Minimum:

BS in Electrical Engineering, Computer Science or related field with 15+ years of Industry experience or MS Electrical Engineering, Computer Science or related field preferred with 12+ years industry experience.
Experience in SoC verification cycle from architecture to tape out to bring up.
Good knowledge of verification methodologies such as UVM/OVM etc.
Hands on ASIC-SoC Design verification tests and debug experience.
Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.
Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).
Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM).
Passionate about AI and thriving in a fast-paced and dynamic startup culture.

Preferred:

Experience with C/C++, SystemC (a big plus!)
Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

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Average salary estimate

$175000 / YEARLY (est.)

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max

$150000K

$200000K

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What You Should Know About Design Verification Engineer, Senior Staff, d-Matrix

Join our dynamic team at d-Matrix as a Design Verification Engineer, Senior Staff, where you'll be stepping into an exciting role at the cutting edge of generative AI technology. Based in our Santa Clara, CA headquarters, we are on the lookout for seasoned professionals who share our passion for pushing boundaries in hardware and software innovation. In this position, you'll collaborate with a highly experienced team on industry-leading programmable in-memory computing architecture that spans a multitude of applications, from cloud to edge. Your expertise will shape not just our company’s present but also its future as you dive into the SoC verification cycle from architecture to tape-out and beyond. We're committed to nurturing a culture that emphasizes respect, inclusiveness, and transparency, where learning is key and challenges are tackled collaboratively. Here, your ideas won’t just be welcomed; they’ll be essential in helping us build a long-lasting legacy in the AI industry. If you're someone who thrives in fast-paced, dynamic environments and is driven by the desire to innovate, we want to hear from you! At d-Matrix, we believe in the potential of every team member and are excited to offer this unique opportunity to hone your skills and make a global impact in technology. Ready to embark on this journey? Let’s redefine the possibilities of AI together!

Frequently Asked Questions (FAQs) for Design Verification Engineer, Senior Staff Role at d-Matrix

What are the key responsibilities of a Design Verification Engineer, Senior Staff at d-Matrix?

As a Design Verification Engineer, Senior Staff at d-Matrix, you will be responsible for the SoC verification cycle from architecture all the way to tape-out and bring-up. You'll work closely with a talented team on our innovative programmable in-memory computing architecture. This includes utilizing your expertise in verification methodologies such as UVM/OVM, and engaging in hands-on ASIC-SoC design verification tests and debug. Your role will also involve creating and implementing verification environments, ensuring the highest standards of quality and effectiveness in our projects.