Job details

Design for Testability (DFT) Architect

About us:

Aeva’s mission is to bring the next wave of perception to a broad range of applications from automated driving to industrial robotics, consumer electronics, consumer health, security, and beyond. Aeva is transforming autonomy with its groundbreaking sensing and perception technology that integrates all key LiDAR components onto a silicon photonics chip in a compact module. Aeva 4D LiDAR sensors uniquely detect instant velocity in addition to 3D position, allowing autonomous devices like vehicles and robots to make more intelligent and safe decisions.

Role Overview:

We are looking for an SoC DFT Architect with experience in mixed-signal/high-performance digital DFT and Functional Safety.

What you'll be doing:

As an SoC DFT Architect you’ll be responsible for defining and/or overseeing, advanced design-for-test (DFT) methodologies for highly-complex digital and/or mixed-signal chips and/or IPs. You will have the opportunity to work with the rest of the team to document DFT specifications, and also develop DFT methodologies and infrastructure. In this role, you'll oversee the definition, development and verification of a consistent methodology for DFT across the whole SoC.

What you'll have:

2-5 years’ experience writing RTL code in Verilog and/or VHDL
2-5 years of verification experience
Broad domain knowledge of DFT including Scan/ATPG, MBiST, LBiST, JTAG, TAP, IO BiST, Analog BiST, etc..
In depth knowledge of EDA tools used in DFT.
Lab debug and DFT bringup experience
Ability to deliver results in a very fast-moving environment
Desire to learn & implement groundbreaking new hardware technology
Excellent communication and organization skills.