Substrate IC Package Layout Design Engineer
Substrate IC Package Layout Design Engineer
About Etched
Etched is building AI chips that are hard-coded for individual model architectures. Our first product (Sohu) only supports transformers, but has an order of magnitude more throughput and lower latency than a B200. With Etched ASICs, you can build products that would be impossible with GPUs, like real-time video generation models and extremely deep & parallel chain-of-thought reasoning agents.
Role Summary
As a Substrate IC Package Layout Design Engineer, you will be responsible for the end-to-end design of complex IC substrate packages, supporting high-power consumption and high-speed signaling. The ideal candidate will have extensive experience with large substrate designs (>50mm), complex power delivery networks, and high-speed signaling solutions (up to and beyond 50GHz). You will work closely with silicon, signal integrity, power integrity, and system help co-design world class substates with OSAT providers. Intense focus on optimization for power delivery through substrate, pushing what’s possible.
Key responsibilities
IC Substrate Layout Design
Lead the design and development of complex IC substrate layouts for high-power AI processors and accelerators.
Design large (>50mm) and complex multi-layer substrate packages with high pin counts and dense routing requirements.
Ensure robust power delivery designs capable of supporting >700W custom silicon solutions.
High-Speed Signal Routing & Integrity
Develop high-speed signal routing solutions capable of supporting >50GHz signaling while minimizing signal integrity issues such as loss and crosstalk.
Collaborate with SI/PI engineers to define signal integrity and power integrity requirements and implement solutions in substrate layout.
Advanced Packaging & CoWoS Integration
Optimize CoWoS (Chip-on-Wafer-on-Substrate) interposer designs for thermal and electrical performance.
Work closely with chip design, packaging, and manufacturing teams to ensure design feasibility and manufacturability.
Design Validation & Verification
Perform DRC (Design Rule Check) and LVS (Layout vs. Schematic) verification for all substrate designs.
Develop and maintain design documentation and guidelines for future substrate designs.
Support design reviews and provide technical guidance to junior team members.
You may be a good fit if you have
Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
10+ years of experience in IC substrate layout design for high-performance processors or accelerators.
Extensive experience with large substrate packages (>50mm) and complex high-density layouts.
Proven experience with high-power (700W+) package designs and robust power delivery networks.
Expertise in high-speed signaling design (>50GHz) and mitigating signal integrity challenges (crosstalk, reflections, impedance mismatches).
Strong experience with CoWoS (Chip-on-Wafer-on-Substrate) interposer design and the impact of the substrate design to support CoWos.
Advanced proficiency in Allegro Package Designer (including constraint management, routing, and design verification).
Deep understanding of SI/PI principles and how they apply to package-level design.
Strong analytical skills and ability to work effectively in a fast-paced, cross-functional team environment.
Benefits
Full medical, dental, and vision packages, with 100% of premium covered
Housing subsidy of $2,000/month for those living within walking distance of the office
Daily lunch and dinner in our office
Relocation support for those moving to Cupertino
How we’re different
Etched believes in the Bitter Lesson. We think most of the progress in the AI field has come from using more FLOPs to train and run models, and the best way to get more FLOPs is to build model-specific hardware. Larger and larger training runs encourage companies to consolidate around fewer model architectures, which creates a market for single-model ASICs.
We are a fully in-person team in Cupertino, and greatly value engineering skills. We do not have boundaries between engineering and research, and we expect all of our technical staff to contribute to both as needed.
Average salary estimate
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As a Substrate IC Package Layout Design Engineer at Etched, you’ll have the opportunity to work on cutting-edge AI chips designed specifically for unique model architectures. Imagine being part of a team that creates high-performance ASICs, such as our Sohu product, which demonstrates extraordinary throughput and minimal latency—something that conventional GPUs simply can’t achieve. In this role, you will lead the design of complex IC substrate packages tailored for high-power and high-speed applications, collaborating closely with silicon and signal integrity teams to push the limits of what’s possible in substrate design. You will be tackling intricate design challenges such as robust power delivery networks that can handle up to 700W, and advanced high-speed signal routing exceeding 50GHz. Your expertise will not only focus on developing optimal substrate layouts but also on ensuring that these designs are practical and manufacturable, all while supporting substantial multi-layer complexities. We pride ourselves on fostering an environment where each team member’s contribution is valued, so if you are driven by innovation and eager to work with a team that prioritizes engineering excellence, this is the perfect role for you. Join us at Etched to redefine the future of AI through specialized hardware design!
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