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Senior Layout Design Engineer

Celestial AI is a Machine Learning (ML) accelerator company that has developed a proprietary technology platform which enables the next generation of high-performance computing solutions. Our mission is to transform data parallel computing with a proprietary Photonic Fabric™ technology platform which uses light for data movement both within chip and between chips. Celestial AI has assembled a highly experienced team of industry leaders who have a track record of building multiple successful technology businesses and just recently announced our Series A funding accelerate our growth. The company's Orion AI accelerator products serve an addressable market that is projected by Omida to exceed $70 billion in 2025.

Job Description:


In this position you will play a key role in contributing to the development of advanced mixed signal layout for low power, high-speed, SERDES, sensors, PLL and other macros to be used in numerous products from high performance data center SOCs to low power consumer SOCs.

You will join a highly collaborative team, and your success will have a significant impact on our products


ESSENTIAL DUTIES AND RESPONSIBILITIES:

  • Layout design of advanced SERDES and other analog and mixed signal macros in deep nanometer- level Fin-FET technologies
  • Tasks include planning and implementing block-level floor-planning, power distribution network, clock and signal routing, analog and mixed signal transistor level layout
  • DRC, LVS and other physical verification tools
  • Participate in post-layout circuit performance analysis
  • Perform physical layout for custom structures in state-of-the-art nanometer-level CMOS technologies using Cadence tools.
  • Assist in taking part in floor planning, custom layout and verifying against design rules and schematics.
  • Learn and ramp on new tools and methodologies
  • Develop realistic schedule for block-level layout including complete verifications

QUALIFICATIONS:

  • At least 10 years of hands-on layout design experience
  • Experience in layout of high-speed SerDes blocks and PLLs in advanced Fin-FET process
  • Good understanding of clock routing and shielding
  • Good understanding of analog and mixed signal layout fundamentals, IR, EM, self and coupling capacitances, RC delay and self-heating
  • Excellent team player

Location: This role can be based out of Santa Clara, CA, Orange County, CA or Toronto, Ontario, Canada


For California location:

As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. The target base salary for this role is approximately $135,000.00 - $155,000.00. The base salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.


#LI-Onsite

We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.

Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.

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We’re on a mission to empower hiring teams large and small to access top talent without any friction. At the same time, Celential also helps accelerate the career potential of engineering and sales candidates. It’s a win-win! Our solutions are po...

18 jobs
TEAM SIZE
DATE POSTED
March 28, 2023

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