SMTS Silicon Design and Verification Engineer

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SMTS SILICON DESIGN AND VERIFICATION ENGINEER

THE ROLE:
Central DFX (CDFX) is a centralized ASIC design group within AMD's Technology and Engineering organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for leading edge AMD products. It is also responsible for DFX design methodology and automation tools development to support the global DFX engineering teams across AMD.

THE PERSON:
As a SMTS Silicon Design Engineer, you will be working with a diverse team of design engineers and managers from various global design locations on design-for-test (DFx) design and verification, project execution and continuous improvement initiatives. This role provides an excellent growth opportunity for robust individuals looking to make a difference. This is an exciting time to join the AMD team!

KEY RESPONSIBLITIES:

• Implementation and verification of DFT architecture and features

• Demonstrated DFD design skills and project execution experience
• 
  Self-starter, driven and disciplined with a dedication to meeting deadlines
• 
  Developing test plans and SV/UVM based Verification environment.
• Run regressions , Triage and debug regression failures.
• Writing Functional Coverage, Checkers , Agents, Scoreboards etc.
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  Used to working independently, and yet can work collaboratively with various levels and organization functions.
  

PREFERRED EXPERIENCE:

• Minimum 7+ years of ASIC or IP Verification experience
• Excellent communication and interpersonal skills
  
• Excellent debugging skills and knowledge on CPU debug Architecture.
  
• Understanding of Design for Test methodologies and DFT verification experience (eg. IEEE1500, JTAG 1149.x, Scan, memory BIST etc.)
• Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
• Strong Verilog, SystemVerilog, C/C++, Perl/Ruby/shell scripts programming skills
• Experience with UVM
• Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards.
• Technical verification leader for a small/mid-d team is a plus

ACADEMIC CREDENTIALS:

• Bachelors or Masters degree in computer engineering/Electrical Engineering

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Benefits offered are described: .
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants' needs under the respective laws throughout all stages of the recruitment and selection process.