Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering)

SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.SR. SOC/ASIC TIMING SIGNOFF & FRONT-END IMPLEMENTATION ENGINEER (SILICON ENGINEERING)At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to 3M+ users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation ASICs for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.RESPONSIBILITIES:• Full chip and block level timing signoff and convergence through timing ecos on post routed database for various timing signoff checks• Full chip and block level front-end implementation from timing constraints development, synthesis, formal verification, power intent generation & validation• Develop block and full chip level timing constraints for test modes• Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)• Analysis of clock domain crossing paths at block and full chip level• Work with mixed signal IP/PLL/SerDes/PHY teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL• Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post synthesis timing validation flows• Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification• Implement Functional ECOs for complex blocks• Deploy and enhance methodology and flows related to timing constraint generation and verification and timing closure• Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route• Work with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design process