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Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) image - Rise Careers
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Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer (Silicon Engineering) - job 1 of 3

SpaceX is seeking a motivated Sr. SOC/ASIC Timing Signoff & Front-End Implementation Engineer to develop cutting-edge next-generation ASICs that will enhance connectivity globally through the Starlink network.

Skills

  • ASIC design flow
  • Timing closure techniques
  • Scripting in Python or Perl
  • Knowledge of low-power methodologies
  • Experience with physical synthesis tools

Responsibilities

  • Full chip and block level timing signoff and convergence checks
  • Timing constraints development and block-level front-end implementation
  • Ownership of timing closure throughout the project cycle
  • Analysis of clock domain crossing paths
  • Collaboration with various teams for integration and verification

Education

  • Bachelor's degree in electrical engineering, computer engineering or computer science

Benefits

  • Competitive salary
  • Health insurance
  • 401(k) plan
  • Opportunities for professional development
  • Dynamic work environment
To read the complete job description, please click on the ‘Apply’ button
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Average salary estimate

$150000 / YEARLY (est.)
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$120000K
$180000K

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1757 jobs
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BADGES
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CULTURE VALUES
Mission Driven
Social Impact Driven
Passion for Exploration
Reward & Recognition
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
SALARY RANGE
$120,000/yr - $180,000/yr
EMPLOYMENT TYPE
Full-time, on-site
DATE POSTED
April 3, 2025

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