DEG/IMSG seeks an experienced pre-Si verification engineer for its PCIe IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments. We are looking for an enthusiastic individual with a strong background in all aspects of IP development and a proven capacity for understanding new technologies, to help deliver on our charter as Intel's center of innovation for IO and Accelerator technologies.
You will be responsible for, but not limited too. Working with a high performing team to deliver fully functional IPs on Intel's latest process technology to reduce product risk for various enterprise IPs including PCI express and accelerators. Interfacing with architects and senior design/val team members to develop new features.
Roles and responsibilities
Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches (BFM, Scoreboard, tests) , and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.
Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification
Qualification
Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 10+ years' experience
-OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 8+ years of experience
-OR- PhD degree in Electrical, Electronics, Computer Engineering with 5+ years of experience.
Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage.
The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions. Experience in BFM development.
Work Model for this Role
This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.
Are you an experienced IP Design Verification Engineer looking for an exciting opportunity in Bangalore, India? Join Intel's PCIe IP development organization, where innovation meets execution. We’re seeking a passionate individual like you, equipped with a robust background in IP development and a knack for grasping new technologies. In this role, you will collaborate with a top-performing team dedicated to delivering cutting-edge functional IPs in Intel’s latest process technology, aimed at reducing product risk for various enterprise IPs, including PCI Express and accelerators. Your day-to-day responsibilities will include performing functional verification of IP logic, developing comprehensive verification plans, and running system simulations to ensure compliance with microarchitecture specifications. You will also interface with architects and design/validation team members to implement new features while documenting test plans and promoting technical reviews. This dynamic position requires a strong educational background in electrical, electronics, or computer engineering, alongside proven experience in verification methodologies, particularly with SystemVerilog and UVM. If you’re ready to enhance verification infrastructure and embrace the challenge of delivering excellent IP designs, we want to hear from you!
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