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IP Design Verification Engineer - job 2 of 2

Job Details:

Job Description: 

DEG/IMSG seeks an experienced pre-Si verification engineer for its PCIe IP development organization, a dynamic team with a history of outstanding execution and industry-leading accomplishments. We are looking for an enthusiastic individual with a strong background in all aspects of IP development and a proven capacity for understanding new technologies, to help deliver on our charter as Intel's center of innovation for IO and Accelerator technologies.

You will be responsible for, but not limited too. Working with a high performing team to deliver fully functional IPs on Intel's latest process technology to reduce product risk for various enterprise IPs including PCI express and accelerators. Interfacing with architects and senior design/val team members to develop new features.

Roles and responsibilities

Performs functional verification of IP logic to ensure design will meet specification requirements. Develops IP verification plans, test benches (BFM, Scoreboard, tests) , and the verification environment to ensure coverage to confirm to microarchitecture specifications. Executes verification plans and defines and runs system simulation models to verify the design, analyze power and timing, and uncover bugs. Replicates, root causes, and debugs issues in the presilicon environment. Finds and implements corrective measures to resolve failing tests. Collaborates with architects, RTL developers, and physical design teams to improve verification of complex architectural and microarchitectural features.

Documents test plans and drives technical reviews of plans and proofs with design and architecture teams. Maintains and improves existing functional verification infrastructure and methodology. Participates in the definition of verification infrastructure and related TFMs needed for functional design verification

Qualifications:

Qualification

Candidate should possess a bachelor's degree in electrical, Electronics, Computer Engineering or Computer Science or any related field with 10+ years' experience

-OR - a Master's degree Electrical, Electronics, Computer Engineering or Computer Science or any related field with 8+ years of experience

-OR- PhD degree in Electrical, Electronics, Computer Engineering with 5+ years of experience.

  • Mandatory Skills :- SV /UVM, Mirco, test bench , test plan creation , coverage analysis , debugging/problem solving  skills .
  • Preferred skills :- BFM development , third party VIP integration , evaluation of VIP’s , formal verification skills and c++
  • Preferred Protocol knowledge on PCIE , Cxl*  ,
  • Solid verbal/written communication skills.o Effective team player with continuous learning mindset.

Be willing to balance multiple tasks. Prior experience in IP development teams would be an added advantage.

The candidate must be able to work independently and be self-motivated to identify, innovate upon, architect and deploy Formal Verification solutions. Experience in BFM development.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

Business group:

The Data Center & Artificial Intelligence Group (DCAI) is at the heart of Intel’s transformation from a PC company to a company that runs the cloud and billions of smart, connected computing devices. The data center is the underpinning for every data-driven service, from artificial intelligence to 5G to high-performance computing, and DCG delivers the products and technologies—spanning software, processors, storage, I/O, and networking solutions—that fuel cloud, communications, enterprise, and government data centers around the world.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$120000 / YEARLY (est.)
min
max
$100000K
$140000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About IP Design Verification Engineer, Intel

Are you an experienced IP Design Verification Engineer looking for an exciting opportunity in Bangalore, India? Join Intel's PCIe IP development organization, where innovation meets execution. We’re seeking a passionate individual like you, equipped with a robust background in IP development and a knack for grasping new technologies. In this role, you will collaborate with a top-performing team dedicated to delivering cutting-edge functional IPs in Intel’s latest process technology, aimed at reducing product risk for various enterprise IPs, including PCI Express and accelerators. Your day-to-day responsibilities will include performing functional verification of IP logic, developing comprehensive verification plans, and running system simulations to ensure compliance with microarchitecture specifications. You will also interface with architects and design/validation team members to implement new features while documenting test plans and promoting technical reviews. This dynamic position requires a strong educational background in electrical, electronics, or computer engineering, alongside proven experience in verification methodologies, particularly with SystemVerilog and UVM. If you’re ready to enhance verification infrastructure and embrace the challenge of delivering excellent IP designs, we want to hear from you!

Frequently Asked Questions (FAQs) for IP Design Verification Engineer Role at Intel
What are the main responsibilities of an IP Design Verification Engineer at Intel?

As an IP Design Verification Engineer at Intel, you will perform functional verification of IP logic, develop verification plans, and create test benches to ensure that every design meets the required specifications. A key part of your role will involve collaborating with architects, RTL developers, and other teams to improve the verification of complex architectural features.

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What qualifications are required for the IP Design Verification Engineer position at Intel?

To qualify for the IP Design Verification Engineer role at Intel, candidates should have a bachelor's degree in electrical, electronics, computer engineering, or computer science, along with significant experience in the field—10+ years for a bachelor's, 8+ for a master's, or 5+ for a PhD holder. You should also be well-versed in SystemVerilog, UVM, and have skills in test bench creation and debugging.

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What skills are preferred for the IP Design Verification Engineer role at Intel?

In addition to the mandatory skills like SystemVerilog and UVM, preferred skills for the IP Design Verification Engineer role at Intel include BFM development, third-party VIP integration, and formal verification skills. Knowledge of protocols such as PCIe and CXL is also advantageous.

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What kind of work environment can an IP Design Verification Engineer expect at Intel?

An IP Design Verification Engineer at Intel can expect a hybrid work model, which allows you to balance on-site and off-site work. This flexibility enables you to maintain productivity while fostering collaboration within a dynamic team focused on innovation in data-centric solutions.

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What does the career growth look like for an IP Design Verification Engineer at Intel?

Intel promotes a culture of continuous learning and career advancement for IP Design Verification Engineers. With opportunities to work on cutting-edge technologies and methodologies, employees can expand their skills and take on leadership roles within the engineering teams, all while contributing to Intel’s transformative vision.

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Common Interview Questions for IP Design Verification Engineer
Can you explain your experience with SystemVerilog and UVM for IP verification?

When addressing your experience with SystemVerilog and UVM, focus on specific projects where you implemented test benches and verification plans. Highlight how you utilized UVM methodologies to enhance coverage and ensure compliance with microarchitecture specifications.

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How do you handle debugging in a presilicon environment?

In response to debugging in a presilicon environment, discuss your approach to replicating and root-cause analysis of issues. Provide examples of how you used systematic methods to identify problems, applied corrective measures, and ensured that tests passed successfully.

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What strategies do you follow to effectively communicate within a cross-functional team?

Describe your communication strategies by emphasizing how you engage with architects and design teams. Provide instances where you documented your verification processes and shared test plans to promote transparency and collaborative problem-solving.

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How do you prioritize tasks when managing multiple verification projects?

When discussing task prioritization, explain your methodology for assessing project deadlines and severity. Share examples of how you balance multiple responsibilities to meet goals efficiently while maintaining high standards in your verification work.

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Can you provide an example of a challenging verification problem you've encountered and how you resolved it?

When presenting a challenging verification problem, narrate a specific situation, detailing the steps you took to analyze the issue, the collaborative effort with your team, and the ultimate outcome. Stress the importance of innovation in finding a resolution.

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What is your experience in developing verification infrastructure?

Explain your experience with verification infrastructure development by detailing specific tools or methodologies you've implemented. Discuss how these improvements enhanced test coverage and efficiency in the verification process.

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What role does test plan documentation play in your verification methodology?

Discuss the critical role of test plan documentation in ensuring accurate verification results. Highlight how it serves as a reference for collaboration and as a roadmap that guides your verification efforts toward meeting design specifications.

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How do you stay updated with the latest technologies and methodologies in IP verification?

Share your commitment to lifelong learning by mentioning resources such as online courses, workshops, and professional communities that you actively participate in. Emphasize your curiosity and eagerness to integrate new knowledge into your work as an IP Design Verification Engineer.

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What do you consider to be the key qualities of an effective IP Design Verification Engineer?

When describing key qualities, focus on traits such as strong analytical skills, effective communication, a collaborative spirit, and a relentless pursuit of excellence. Illustrate how these qualities contribute to successful verification outcomes and project progress.

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Why do you want to work as an IP Design Verification Engineer with Intel?

When asked why you want to work at Intel, convey your enthusiasm for the company’s innovative spirit and the opportunity to contribute to groundbreaking projects. Describe how Intel's mission aligns with your professional goals and how you can bring value to the team.

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CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
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SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
April 11, 2025

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