Design for Test Engineer - RISC-V - Contractor

A Design for Test Engineer at Tenstorrent is responsible for implementing DFT features into RTL using Verilog, optimizing DFT architectures, and performing ATPG and test coverage analysis. You'll also conduct gate-level simulations and support silicon bring-up, working closely with test engineering for planning and pattern generation.

To qualify for the Design for Test Engineer position at Tenstorrent, candidates should possess a BS/MS/PhD in Electrical Engineering or related fields, along with 5+ years of industry experience in advanced DFx techniques. Familiarity with industry-standard ATPG tools, strong RTL coding skills, and knowledge of low-power design techniques are also essential.

In the Design for Test Engineer role at Tenstorrent, you will work with industry-standard tools for ATPG and DFx insertion, conduct gate-level simulations using Synopsys VCS and Verdi, and utilize SystemVerilog and UVM for efficient design implementation.

As a Design for Test Engineer at Tenstorrent, you will engage in high-performance DFT implementations within AI and ML architectures, contributing to the development of our RISC-V CPU. Your role will include optimizing test quality and minimizing intrusions on the design while collaborating with other ASIC design engineers.

Tenstorrent offers a competitive compensation package for the Design for Test Engineer position, with salaries ranging from $100k to $500k, depending on experience, skills, and education, along with variable compensation. Benefits and pay equity are important to us, making Tenstorrent an attractive place to build your career.

When answering, be specific about your past projects where you implemented DFT features using Verilog. Highlight your understanding of DFT methodologies, the types of designs you worked on, and how your contributions improved testability.

Discuss your approach to optimizing DFT architectures, focusing on balancing test coverage and test cost. Mention specific techniques like scan compression and JTAG implementation to demonstrate your proficiency in the role.

Explain the tools you’ve used for ATPG and how you analyze test coverage results. Provide examples of how your analysis led to improved designs or yields, showcasing both your technical knowledge and results-driven mindset.

Share examples of low-power design techniques you have applied in previous projects. Discuss how your knowledge of power gating or multi-Vt design has positively impacted your designs' performance and efficiency.

Talk about your experience with tools like Synopsys VCS and Verdi, and discuss the importance of gate-level simulation in verifying DFT implementations. Share any challenges you faced and how you overcame them.

Discuss your role in silicon bring-up projects, detailing your methods for debugging issues that arise. Illustrate this with specific examples of how you ensured the success of previous silicon bring-up efforts.

Highlight your hands-on experience with SystemVerilog and UVM, explaining how you used these tools in previous projects for creating testbenches or implementing DFT logic. Showcase your understanding of their roles in the design process.

Provide insights into specific challenges you faced when working with fault models, how you identified those challenges, and the solutions you implemented. This shows your problem-solving skills and technical expertise.

Emphasize your commitment to continuous learning in the field by mentioning industry publications, conferences, workshops, or online courses you engage with regularly.

Use this opportunity to share quantitative examples of how your contributions led to improved test yields in prior projects, which demonstrates your impact as a Design for Test Engineer.