Job details

SoC/ASIC Design Verification Engineer

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zeroRISC

zeroRISC is redefining chip security and supply chain integrity by empowering device owners and operators in crucial sectors like silicon production, IoT, and critical infrastructure with full device ownership, control, and visibility. Led by the founders of the OpenTitan secure silicon project, zeroRISC is driving commercial adoption of high assurance software and services rooted in open silicon. Our products forge an immutable connection between hardware and software, enabling users to trust their devices no matter where they’re built or where they’re deployed.

Role Overview

As a zeroRISC SoC/ASIC Design Verification Engineer, you will develop, verify, and maintain silicon in security-sensitive settings, including root-of-trust technology. You will elevate and solidify zeroRISC's status as the leading provider of secure silicon IP by developing essential verification collateral. You will interact directly with zeroRISC customers to understand their requirements and deliver solutions benefitting both customer and zeroRISC alike. You will participate in the whole chip design process from architecture to tapeout and silicon validation. By engaging with the world's premier open-source silicon community, you will support our mission of open secure silicon everywhere. We're looking for engineers with strong design verification skills (and a long view of secure system architecture) who are also fast, flexible learners and enthusiastic about open source.

Key Responsibilities:

Verify ASIC/SoC functionality, performance, security, and power throughout the full chip design life cycle, from test plan definition to sign-off
Build high quality verification environments at the chip/top and block levels following engineering best practices
Write thorough verification documentation including test plans
Diagnose, debug, and resolve regression failures and other errors
Achieve coverage closure
Ensure design functionality while upholding stringent timelines in collaboration with architecture, design, software, system, and silicon validation teams as well as engineering program managers

What We’re Looking For:

Bachelor’s degree in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
4 years of experience with simulation-based verification methodologies and languages such as UVM and SystemVerilog or formal verification-based techniques including industry standard tools
Experience developing and maintaining testbenches, test cases, and verification environments for simulation-based verification or formal verification environments

Preferred Qualifications (not required):

Master’s or PhD in Electrical Engineering or Computer Science, or a related technical field or equivalent experience
Knowledge of security ASICs or accelerators (e.g. cryptography accelerators or GPUs)
Knowledge of computer architecture and memory subsystem architectures
Experience verifying low power designs
Experience with scripting languages such as Python

Why Join Us?

Your work will directly contribute to the development of cutting-edge security solutions, protecting critical systems in industrial and IoT environments
As a seed-stage startup, this role offers significant opportunities for learning and career growth
Join a close-knit, innovative team where you can learn, grow, and contribute to building something meaningful in the security space

Average salary estimate

$115000 / YEARLY (est.)

min

max

$100000K

$130000K

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What You Should Know About SoC/ASIC Design Verification Engineer, zeroRISC

At zeroRISC, we're all about redefining chip security and integrity in the evolving landscape of technology. As a SoC/ASIC Design Verification Engineer, you'll play a pivotal role in enhancing our mission. Picture yourself diving deep into the world of silicon production, IoT, and critical infrastructure, ensuring device owners have full control and trust in their technologies. In this position, you’ll be responsible for developing, verifying, and maintaining silicon within security-sensitive environments, particularly focusing on root-of-trust technologies. You'll leverage your strong design verification skills to interact directly with our customers, gaining insights into their needs and delivering tailored solutions that benefit both parties. Your day-to-day will involve verifying ASIC/SoC functionality throughout the entire chip lifecycle, from drafting test plans to final sign-off. Plus, you’ll collaborate across teams, engaging with the top minds in the open-source silicon community. With an emphasis on creating high-quality verification environments, you'll tackle challenges head-on, achieving coverage closure and ensuring functionality aligns with our stringent timelines. If you thrive in fast-paced environments, love learning, and are passionate about open source, we want you on our innovative team!

Frequently Asked Questions (FAQs) for SoC/ASIC Design Verification Engineer Role at zeroRISC

What are the key responsibilities of a SoC/ASIC Design Verification Engineer at zeroRISC?

As a SoC/ASIC Design Verification Engineer at zeroRISC, your primary responsibilities will include verifying ASIC/SoC functionality and performance throughout the chip design life cycle, creating high-quality verification environments, writing detailed verification documentation, and diagnosing and resolving errors. You'll also engage with various engineering teams to ensure design functionality while meeting tight deadlines.