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EDA Design Flow Development Engineer - job 1 of 2

Job Details:

Job Description: 

About The Group

Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process/packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona.

About The Role

The Design Technology Platform (DTP) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs), foundational IPs (FIPs), and the Intel Foundry reference flows. These same deliverables carry out technology lead vehicle execution for Si validation. Enablement and optimization of reference flows and design flows on Intel technology play a crucial role in accomplishing DTP's charter.

The design flow development engineer will work in a team responsible for architecting, executing, and delivery of the EDA design flow for all DTCO activities, technology lead vehicle design, IP design, and product design in TD. The design flow will be built on top of a reference flow enabled on Intel technology and released from external EDA vendors. The design flow covers all aspects of front-end and back-end design from RTL to GDS, digital and analog, design creation, verification, and signoff.

Required Experience

  • Experience in the development of EDA tools, flows and/or design env for digital or analog designs with demonstrated strong programing skills.
  • Working knowledge in digital and/or analog Si design and methodology.
  • Prior experience in EDA tool/flow and design environment development is highly desirable.
  • Familiarity with automated SoC design methodology and/or analog/mixed-signal design methodology is a big plus.
  • Result-oriented and capable of disciplined flow execution to meet delivery milestones in a fast-paced environment on advanced technology nodes.
  • Excellent written and verbal communication skills.

Preferred Experience

  • Working knowledge with major (EDA) software platforms (Synopsys, Cadence, Siemens).
  • Working knowledge of all aspects of digital SoC in a product setting – floor planning, RTL design, logic synthesis, place and route, clock tree construction, extraction and timing signoff, signal integrity analysis, layout and reliability verification, and full chip integration.
  • Working knowledge of key aspects of Analog tools - schematic entry, custom layout editing, extraction, simulation, reliability, and signoff.
  • Demonstrated experience in establishing and qualifying digital or analog design flow from an EDA reference flow and addressing product specific design/methodology requirements and design database management.
  • Demonstrated ability to understand and interpret industry EDA trends in response to advanced node requirements, drive design flow initiatives to align.

Qualifications:

  • BS, MS, or PhD degree in electrical engineering, computer engineering or similar field.
  • BS + 15 years or M.S./Ph.D. + 12 years of experience in the development of EDA tools, flows and/or design env for digital or analog designs with demonstrated strong programing skills.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Santa Clara

Additional Locations:

US, Arizona, Phoenix

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support.  Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$214,730.00-$303,140.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$258935 / YEARLY (est.)
min
max
$214730K
$303140K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About EDA Design Flow Development Engineer, Intel

Are you ready to be at the forefront of technology development with Intel as an EDA Design Flow Development Engineer? Situated in the heart of Santa Clara, California, this role places you in an innovative environment that's pivotal to advancing Moore's Law. You'll play a vital role in the Design Technology Platform team, working closely with technology experts to enhance our cutting-edge processes and packaging technologies. Imagine being responsible for architecting and executing the EDA design flow that aids in everything from digital to analog designs. Your work will encompass the entire design spectrum, from RTL all the way through to GDS, facilitating both design creation and verification. We're looking for someone with a robust programming background and experience in EDA tools and flows. Prior knowledge of digital and analog silicon design is a plus, but it's your passion for result-oriented execution that will make you shine in our fast-paced environment. Collaborating with external EDA vendors, you'll help optimize reference flows and support delivery milestones. Whether you're producing Process Design Kits or foundational IPs, your contributions will help shape the next generation of technology. If you're eager to leverage your expertise to drive product design and technology advancement while enjoying the support of industry leaders, then this opportunity at Intel is perfect for you!

Frequently Asked Questions (FAQs) for EDA Design Flow Development Engineer Role at Intel
What are the primary responsibilities of the EDA Design Flow Development Engineer at Intel?

The EDA Design Flow Development Engineer at Intel is primarily responsible for architecting, executing, and delivering EDA design flows for various design types, including digital and analog. You'll engage with Design Technology Co-Optimization (DTCO) efforts, working closely with other teams to maximize the value of Intel's technology. Your role also involves development and verification processes, ensuring that the design flows meet fast-paced delivery milestones in an advanced technology environment.

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What qualifications are necessary for the EDA Design Flow Development Engineer position at Intel?

To be considered for the EDA Design Flow Development Engineer position at Intel, candidates should have a Bachelor's, Master's, or Ph.D. degree in electrical engineering, computer engineering, or a similar field. Additionally, you’ll need significant experience, with a minimum of BS + 15 years or MS/PhD + 12 years in developing EDA tools and design flows for digital or analog designs, along with strong programming skills.

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What skills are essential for success as an EDA Design Flow Development Engineer at Intel?

An EDA Design Flow Development Engineer at Intel should possess strong programming skills and expertise in EDA tool development and flow management. Knowledge of digital and analog silicon design methodologies, familiarity with SOC design methodologies, and the ability to execute processes in a disciplined manner are also crucial. Communication skills are key since collaboration with various teams is a regular part of the job.

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Is experience with specific EDA tools a requirement for the EDA Design Flow Development Engineer position at Intel?

Yes, having a working knowledge of major EDA software platforms such as Synopsys, Cadence, and Siemens is highly beneficial when applying for the EDA Design Flow Development Engineer position at Intel. Familiarity with the complete digital SoC design process, along with analog design tools, will significantly enhance your candidacy.

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What does the team dynamic look like for the EDA Design Flow Development Engineer role at Intel?

As an EDA Design Flow Development Engineer at Intel, you will be part of a collaborative team within the Design Technology Platform. This role involves working with technology teams and external EDA vendors, fostering a cooperative environment focused on innovation and excellence. You’ll be encouraged to share your insights, drive initiatives, and provide support to your colleagues throughout project developments.

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Common Interview Questions for EDA Design Flow Development Engineer
Can you describe your experience with EDA tools in the context of design flow development?

When answering this question, provide specific examples of EDA tools you have used and the context in which you utilized them. Highlight projects or tasks where your knowledge contributed to successful design flow development, and share how you addressed challenges within your role.

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What do you know about the Design Technology Co-Optimization process?

Discuss your understanding of DTCO, focusing on how it allows for enhanced collaboration to optimize both design technology and manufacturing processes. Mention any personal experiences you've had with the DTCO process in your previous roles and its impact on project outcomes.

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How would you approach architecting a new EDA design flow for a complex project?

Describe a systematic approach you would take to architect a new EDA design flow. You might want to include an assessment of project requirements, collaboration with stakeholders, or the integration of existing tools and methodologies to achieve the project goals effectively.

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What methods do you use to ensure timely delivery of design flow developments?

Share techniques or methodologies that you employ to track project timelines and manage deliverables. This could involve using project management tools, setting milestones, and maintaining open communication with team members to address any issues proactively.

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Discuss your experience with both digital and analog design methodologies.

Be prepared to discuss specific projects where you worked on digital and analog designs. Highlight the methodologies you used, the challenges you faced, and how you overcame them, especially in terms of flow execution and integration.

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What are the key considerations when addressing product-specific design requirements?

In your response, mention the importance of understanding the unique needs of the product and how these inform the design methodology. Talk about the necessity of tailoring design flows to meet these requirements while also ensuring compatibility with existing frameworks and tools.

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How do you keep current with trends in EDA and semiconductor technology?

Discuss your commitment to continuous learning through resources like industry publications, webinars, and conferences. Sharing any personal experiences or insights from attending industry events can add value to your response.

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Can you provide an example of a successful collaboration with external partners, such as EDA vendors?

Be ready to share a specific example that demonstrates your ability to work with EDA vendors. Focus on how effective communication and collaboration helped meet project requirements, resolve issues, or innovate new solutions.

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What is your approach to troubleshooting within the EDA environment?

Explain your systematic method for diagnosing and troubleshooting issues within EDA tools and flows. Include an example of a challenging situation you've encountered and how you resolved it, demonstrating your analytical skills and problem-solving abilities.

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How do you measure the success of a design flow you've developed?

In your answer, focus on metrics that indicate success, such as reduced cycle times, improved design quality, or increased efficiency. Using examples from your experience to illustrate how you assessed the effectiveness of your design flows will strengthen your response.

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MATCH
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BADGES
Badge ChangemakerBadge Diversity ChampionBadge Flexible CultureBadge Global CitizenBadge Work&Life Balance
CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
April 17, 2025

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