Everactive is developing maintenance-free wireless sensing systems for industrial environments. Utilizing revolutionary ultra-low-power digital & RF circuit technologies (from U of M & UVA) and innovative communications protocols, Everactive's products can go anywhere, require no batteries, and enable new data streams and insights that unlock real value in traditional Operating Technology environments.
We are looking for an outstanding Senior SoC Design engineer who is passionate about designing, building and debugging ultra-low-power systems-on-chip for our cutting edge batteryless sensors. You will join our digital team that architects and builds our SoCs all the way from system-level concepts to tape-out and post-silicon support. You will face the challenges of pushing the digital portion of our mixed signal designs to run at near and sub-threshold levels to allow the overall system to operate effectively in an energy-harvesting battery-less environment.
You will help the team:
Collaborate with firmware, board, and analog designers to ensure the SoC as a whole will meet the functional requirements
Propose and build the SoC architecture, and define requirements for sub-blocks
Understand the different use cases for the system, and develop code/test cases to exercise and verify those use cases
Review timing closure reports and power analysis reports, and identify areas to improve power/performance at the all levels (architecture, RTL, synthesis...)
Review and support firmware development for applications running on the SoC
You will bring:
Experience with system-level architecture and block definition
Experience in writing and debugging Verilog/SystemVerilog
Experience in testing (bench validation) and debugging silicon bugs
Experience writing timing constraints, static timing closure
Experience with clock domain crossing design and verification
Experience with gate level simulations
Excellent communication and collaboration skills
Excellent documentation skills
Experience with the following is a plus:
Low power synthesis (UPF/CPF, CLP), place and route tools
FPGA synthesis and implementation
UVM verification
Good understanding of C/C+ for embedded devices
Automation skills using Python (or Perl) Language
The ideal candidate's technical background will include a Bachelor's degree or greater in Electrical Engineering at least 10 years of proven experience in developing, testing and debugging ASICs
Successful Everactive employees routinely exhibit our four core values:
Everactive is an equal opportunity employer, and we value diversity in all its forms. We do not discriminate on the basis of race, religion, color, national origin, gender identity, sex, sexual orientation, gender identity, age, marital status, genetic information, veteran or disability status.
We are committed to recruit, hire, and develop an exceptional team of individuals aligned by a common vision of the future of computing. We recognize that our team is strongest when we respect and embrace differences while cultivating a culture of inclusion across race, gender, age, religion, identity, orientation, beliefs, and life experiences that make us unique. Our diversity is what drives our greatest achievements.
We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform essential job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.
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Everactive brings self-powered intelligence to the physical world. Operating without batteries, the company’s always-on wireless sensors deliver continuous cloud-based analytics at a scale not possible with battery-powered devices. Everactive’s en...
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