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Design Verification Engineer, Staff

At d-Matrix, we are focused on unleashing the potential of generative AI to power the transformation of technology. We are at the forefront of software and hardware innovation, pushing the boundaries of what is possible. Our culture is one of respect and collaboration.

We value humility and believe in direct communication. Our team is inclusive, and our differing perspectives allow for better solutions. We are seeking individuals passionate about tackling challenges and are driven by execution.  Ready to come find your playground? Together, we can help shape the endless possibilities of AI. 

Location:

Hybrid, working onsite at our Bangalore, India headquarters 3 days per week.

The role: Design Verification Engineer, Senior Staff

What you will do:

We want to build a company and a culture that sustains the tests of time. We offer the candidate a very unique opportunity to express themselves and become a future leader in an industry that will have a huge influence globally. We are striving to build a culture of transparency, inclusiveness and intellectual honesty while ensuring all our team members are always learning and having fun on the journey. We have built the industry’s first highly programmable in-memory computing architecture that applies to a broad class of applications from cloud to edge. The candidate will get to work on a path breaking architecture with a highly experienced team that knows what it takes to build a successful business.

What you will bring:

Minimum:

  • BS in Electrical Engineering, Computer Science or related field with 7+ years of Industry experience or MS Electrical Engineering, Computer Science or related field preferred with 5+ years industry experience.

  • Experience in SoC verification cycle from architecture to tape out to bring up.

  • Good knowledge of verification methodologies such as UVM/OVM etc.

  • Hands on ASIC-SoC Design verification tests and debug experience.

  • Fluency with SystemVerilog randomization constraints, coverage, and assertions methodology.

  • Good problem-solving skills, and the passion to take on challenges (particularly in AI domain).

  • Good experience with SystemVerilog, and verification methodology (UVM/OVM/VMM).

  • Passionate about AI and thriving in a fast-paced and dynamic startup culture.

Preferred:

  • Experience with C/C++, SystemC (a big plus!)

  • Successfully lead creation/implementation of multiple SoC verification environments and tape out efforts.

Equal Opportunity Employment Policy

d-Matrix is proud to be an equal opportunity workplace and affirmative action employer. We’re committed to fostering an inclusive environment where everyone feels welcomed and empowered to do their best work. We hire the best talent for our teams, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. Our focus is on hiring teammates with humble expertise, kindness, dedication and a willingness to embrace challenges and learn together every day.

d-Matrix does not accept resumes or candidate submissions from external agencies. We appreciate the interest and effort of recruitment firms, but we kindly request that individual interested in opportunities with d-Matrix apply directly through our official channels. This approach allows us to streamline our hiring processes and maintain a consistent and fair evaluation of al applicants. Thank you for your understanding and cooperation.

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What You Should Know About Design Verification Engineer, Staff, d-Matrix

At d-Matrix, we're on a mission to unleash the potential of generative AI, and we're looking for a passionate Design Verification Engineer, Senior Staff to join our innovative team in Bangalore. We pride ourselves on a culture built on respect, collaboration, and direct communication, and we believe in the power of diverse perspectives to fuel our creativity and success. As a Design Verification Engineer, you'll have a unique opportunity to contribute to groundbreaking projects while developing your skills and leadership abilities in the fast-paced tech world. Your work will focus on our industry-leading programmable in-memory computing architecture, which is transforming applications from the cloud to edge computing. With a mix of onsite and hybrid work, you'll collaborate closely with a seasoned team dedicated to building a sustainable and inclusive future in technology. If you're excited by the opportunity to tackle challenging problems with a group of like-minded individuals, and thrive in a dynamic environment, we encourage you to dive in and explore the possibilities with d-Matrix!

Frequently Asked Questions (FAQs) for Design Verification Engineer, Staff Role at d-Matrix
What are the key responsibilities of a Design Verification Engineer at d-Matrix?

As a Design Verification Engineer, Senior Staff at d-Matrix, you'll be responsible for overseeing the SoC verification cycle, from architecture and tape-out to the bring-up phase. Your role includes creating and implementing verification tests, debugging, and ensuring that our cutting-edge programmable in-memory computing architecture meets high standards of quality and performance.

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What qualifications are required for the Design Verification Engineer position at d-Matrix?

To excel as a Design Verification Engineer, Senior Staff at d-Matrix, candidates should hold at least a BS in Electrical Engineering or Computer Science with over 7 years of industry experience, or an MS with 5+ years. Key skills include proficiency in verification methodologies like UVM, hands-on ASIC-SoC design verification, and fluency in SystemVerilog.

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How does d-Matrix foster a collaborative environment for Design Verification Engineers?

d-Matrix is committed to creating an inclusive and collaborative work culture. Design Verification Engineers will find a supportive environment that values open communication, teamwork, and diverse perspectives, ensuring that every team member feels empowered to contribute their best work.

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What kind of growth opportunities does d-Matrix offer to its Design Verification Engineers?

At d-Matrix, we believe in nurturing our talent. As a Design Verification Engineer, Senior Staff, you'll have unique opportunities to advance your skills and leadership potential while working on transformative projects in AI and cutting-edge computing, paving the way for your career growth in the tech industry.

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What technologies should a Design Verification Engineer be familiar with when applying to d-Matrix?

Candidates applying for the Design Verification Engineer position at d-Matrix should be well-versed in key technologies, including SystemVerilog, UVM/OVM, and preferably C/C++. Familiarity with the AI domain and experience in leading SoC verification efforts is also highly beneficial.

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Common Interview Questions for Design Verification Engineer, Staff
Can you explain your experience with SoC verification cycles?

When answering this question, focus on specific projects you've worked on, detailing your role in the SoC verification cycle, any methodologies you applied, and the outcomes. Highlight your understanding of each phase, including architecture, tape-out, and bring-up, showcasing your comprehensive knowledge.

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What verification methodologies are you most comfortable with?

Be prepared to discuss your experience with verification methodologies like UVM. Share specific instances where you've applied these methodologies, how you overcame challenges, and the impact it had on your projects to demonstrate your expertise.

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Describe a challenging problem you faced during design verification and how you resolved it.

Utilize the STAR (Situation, Task, Action, Result) method to narrate a past challenge. Emphasize your problem-solving skills and the innovative approaches you took to reach a resolution, ultimately illustrating your capability in tackling difficult tasks.

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How do you approach debugging in ASIC-SoC design verification?

Outline your systematic approach to debugging, including any tools or methodologies you employ. Share specific examples of debugging situations, what you learned, and how it influenced your verification strategies.

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What role does SystemVerilog play in your design verification process?

Discuss your practical experience with SystemVerilog, emphasizing how you use it for randomization constraints, coverage, and assertions. Highlight how it enhances your verification process and any notable outcomes you've achieved.

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How do you stay updated with industry trends in AI and hardware design?

Communicate your commitment to professional development through various channels such as attending workshops, following relevant publications, or participating in online forums. Mention any recent trends or technologies you’ve come across and how they may apply to your role.

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What makes you passionate about joining d-Matrix as a Design Verification Engineer?

Reflect on d-Matrix's mission and culture, aligning your personal values with the company's. Share specific aspects of their work that excite you and outline how your passion for AI and hardware innovation drives your interest in this role.

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Can you detail an experience where you led a verification project?

When discussing leadership, utilize the STAR method to narrate a project you spearheaded. Detail your responsibilities, how you motivated the team, any challenges you faced, and the final results to illustrate your leadership skills.

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What tools do you use to manage design verification tasks effectively?

Mention specific tools that aid your management of design verification, such as simulation software or project management tools. Explain how these tools help streamline your workflow and contribute to project success.

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How do you prioritize tasks when working on multiple verification projects?

Describe your approach to task prioritization, including any frameworks or methods you apply. Give examples of how you have successfully managed competing priorities in past projects without compromising quality or deadlines.

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EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
January 6, 2025

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