Job title:- Hardware Engineer
Location:- Mountain View, CA (Remote can be submitted)
Duration:- 12 Months...
Pay rate:- $80/hr on W2 without any benefits
What candidate will Be Doing:
• At-least 8+ years of experience in System Verilog
• At-least 8+ year of experience in UVM.
• Experience in complete verification cycle which includes development of test plan, BFM/Driver/Monitor/Scoreboard component development and integration in test bench, stress/corner testing, failure debug, gate level simulations, assertions, and coverage closure.
• Proficient in SVTB/UVM
• Proficient in debug and assertions coding
• SOC Verification experience
• Proficient in AXI protocol
• Verification closure with team
• Make/Perl/Python
• Ensure customer satisfaction.
• Reporting to customer on daily or weekly progress effectively