Senior VLSI CAD R&D, Power and Timing Modeling

NVIDIA's continued advancement of world-leading hardware requires a combination of the best of both external and internal EDA tools. Our team develops these highly optimized internal tools by fusing advances in silicon modeling, machine learning, and novel algorithms in C++. We are seeking a CAD R&D Engineer excited to innovate in algorithms for large scale and high accuracy gate-level power, timing, parasitic, and noise analysis. A deep understanding of existing Liberty modeling including CCS, CCSP, CCSN, and LVF is required along with the insight to develop new types of models based on silicon feedback. Some experience in parasitic extraction and/or interconnect modeling is also needed. We particularly focus on high performance algorithms, so proficiency in multithreaded code is ideal.
 

Developing software within a leading hardware company means getting to almost exclusively focus on the latest processes and most advanced designs. We're not bogged down by legacy support, niche roles, or convoluted approval processes. Our developers enjoy unusually high intellectual freedom and the ability to explore broad roles. If you like to work across many technical areas and see your successes directly realized in the world's best AI hardware, this is it!
 

What you’ll be doing:

• Invent and optimize methods to improve the accuracy and capacity of timing, power, and noise models used within a suite of internal optimization tools. These tools already outperform the industry's alternatives in high capacity timing and power optimization and will advance even further with your contributions.

• Develop new ways of modeling device and interconnect physics beyond the capabilities of external EDA tools to better match Vmin and Fmax distributions observed in real silicon.

• Boost the accuracy and efficient application of incremental parasitic estimates used during optimization

• Over time, this role can expand to other areas of physical design implementation and analysis tools

• As with any software engineering team, we do write a lot of code, but this is broader than a typical CAD or EDA role. Instead, we as a team own the whole process from discovery and invention of new optimization opportunities, to developing solutions and working directly inside design teams to facilitate deployment.

What we need to see:

• MS or PhD in Electrical Engineering or Device Physics (or equivalent experience)

• 8+ years experience in gate-level static timing analysis and/or power analysis

• Proficiency in C++

• Strong background of Liberty timing, power, and noise models (CCS, CCSP, CCSN)

• Thorough understanding of interconnect parasitic models and their representation in SPEF

• Good understanding of algorithm design principles such as complexity analysis, efficient memory and I/O use, etc.

Ways to stand out from the crowd:

• Experience with GNNs (Graph Neural Networks) and other relevant machine learning frameworks, especially as applied to device and interconnect modeling

• Expertise in PrimeTime, PrimeTime-PX, NanoTime, SPICE, or other analysis tools

• Background in physical design, timing, and/or power optimization algorithms.

• Experience in mitigating logic glitches in adders and other highly reconvergent logic

• Background in high performance software design including multithreading, distributed computing, and efficient memory use.

NVIDIA is widely considered to be one of the technology world’s most desirable employers, and due to outstanding success, our teams are rapidly growing. Are you passionate about becoming a part of a best-in-class team driving the latest in GPU and AI technology? If so, we want to hear from you!

The base salary range is 168,000 USD - 310,500 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions.NVIDIA is committed to fostering a diverse work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.