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CPU Core Logic Designer

Job Details:

Job Description: 

Do Something Wonderful!

Intel put Silicon in Silicon Valley. No one else is obsessed with engineering and have a brighter future. Every day, we create world changing technology that enriches the lives of every person on earth. So, if you have a big idea, let's do something wonderful together. Join us, because at Intel, we are building a better tomorrow.

Who We Are

We are working on the CPU design in Folsom. The team in Folsom has the frontend team working on ucode, RTL and validation. We also have a backend team working on circuit design, structural design, low power design. Finally, we have a backend integration working on full-chip timing, layout and design integration.

Who You Are

Responsibilities include but are not limited to:

  • Develops the logic design, register transfer level (RTL) coding, and simulation for a CPU required to generate cell libraries, functional units, and the CPU IP block for integration in full chip designs.

  • Participates actively in the definition of architecture and microarchitecture features of the CPU being designed.

  • Applies various strategies, tools, and methods to write RTL and optimize logic to qualify the design to meet power, performance, area, and timing goals as well as design integrity for physical implementation.

  • Reviews the verification plan and implementation to ensure design features are verified correctly and resolves and implements corrective measures for failing RTL tests to ensure correctness of features.

  • Documents micro architectural specs (MAS) of the CPU features being designed. Supports SoC customers to ensure high-quality integration of the CPU block.

Qualifications:

You must possess the minimum education requirements and minimum required qualifications to be initially considered for this position. Relevant experience can be obtained through schoolwork, classes, project work, internships, and/or military experience. Additional preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
 

Minimum Qualifications

  • Bachelor's degree in Electrical/Computer Engineering or Computer Science and 4+ years of experience or a Master's degree in Electrical/Computer Engineering or Computer Science and 3+ years of experience.

  • 3+ combined experience in:

    • System Verilog/Verilog/VHDL and/or VCS or similar Simulator

    • Logic design and/or front end.

    • Computer architecture and microarchitecture.

    • Software/programming languages (i.e. C, C++, C#, Visual Basic/.NET. Perl, Python, Java, etc.).

  • Modern energy-efficient/low-power logic design techniques, including those specifically applicable to high frequency optimization.

Preferred Qualifications

  • Knowledge of Intel Architecture ISA and system architecture, including x86 assembly language.

  • Experience with high-speed circuit design and optimization for Datapath, circuits and/or arrays.

  • Familiarity with circuit planning and timing convergence.

  • Experience working with cross functional teams (Architecture, Spec development, Design, Formal, Verification).

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, California, Folsom

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$161,230.00-$227,620.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will require an on-site presence. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$194425 / YEARLY (est.)
min
max
$161230K
$227620K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

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MATCH
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BADGES
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CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, onsite
DATE POSTED
May 29, 2025

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