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EDA Design Flow Development Engineer - job 2 of 2

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Job Description:

Technology Development (TD) is the heart and soul of Moore's Law at Intel, enabling Intel to create world-changing technology that enriches the lives of every person on earth. TD drives breakthrough research and develops next generation process/packaging technologies, while also running high volume manufacturing operations in its state-of-the-art facilities in Oregon and Arizona. The Design Technology Platform (DTP) team in TD works closely with the technology team to maximize the value proposition of the technology for our customers thru Design Technology Co-Optimization (DTCO), delivers the Process Design Kits (PDKs), foundational IPs (FIPs), and the Intel Foundry reference flows. These same deliverables carry out technology lead vehicle execution for Si validation. Enablement and optimization of reference flows and design flows on Intel technology play a crucial role in accomplishing DTP's charter.

Design flow development engineer will work in a team responsible for architecting, executing, and delivery of the EDA design flow for all DTCO activities, technology lead vehicle design, IP design, and product design in TD. The design flow will be built on top of a reference flow enabled on Intel technology and released from external EDA vendors. The design flow covers all aspects of front-end and back-end design from RTL to GDS, digital and analog, design creation, verification, and signoff. The candidate must be result-oriented and capable of disciplined flow execution to meet delivery milestones in a fast-paced environment on advanced technology nodes. Prior experience in EDA tool/flow and design environment development is highly desirable. Familiarity with automated SoC design methodology and/or analog/mixed-signal design methodology is a big plus.

Required Experience

Experience in the development of EDA tools, flows and/or design env for digital or analog designs with demonstrated strong programing skills.
Working knowledge in digital and/or analog Si design and methodology.

Preferred Experience:

Working knowledge with major (EDA) software platforms (Synopsys, Cadence, Siemens).
Working knowledge of all aspects of digital SoC in a product setting - floorplanning, RTL design, logic synthesis, place and route, clock tree construction, extraction and timing signoff, signal integrity analysis, layout and reliability verification, and full chip integration.
Working knowledge of key aspects of Analog tools - schematic entry, custom layout editing, extraction, simulation, reliability, and signoff.
Demonstrated experience in establishing and qualifying digital or analog design flow from an EDA reference flow and addressing product specific design/methodology requirements and design database management.
Demonstrated ability to understand and interpret industry EDA trend in response to advanced node requirements, drive design flow initiatives to align.
Excellent written and verbal communication skills.

Qualifications:

BS, MS, or PhD degree in electrical engineering, computer engineering or similar field.
BS + 15 years or M.S./Ph.D. + 12 years of experience in the development of EDA tools, flows and/or design env for digital or analog designs with demonstrated strong programing skills.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, Texas, Austin

Additional Locations:

US, Arizona, Phoenix, US, California, Santa Clara, US, Oregon, Hillsboro

Business group:

As the world's largest chip manufacturer, Intel strives to make every facet of semiconductor manufacturing state-of-the-art -- from semiconductor process development and manufacturing, through yield improvement to packaging, final test and optimization, and world class Supply Chain and facilities support. Employees in the Technology Development and Manufacturing Group are part of a worldwide network of design, development, manufacturing, and assembly/test facilities, all focused on utilizing the power of Moore’s Law to bring smart, connected devices to every person on Earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

This role is a Position of Trust. Should you accept this position, you must consent to and pass an extended Background Investigation, which includes (subject to country law), extended education, SEC sanctions, and additional criminal and civil checks. For internals, this investigation may or may not be completed prior to starting the position. For additional questions, please contact your Recruiter.

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$214,730.00-$303,140.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$258935 / YEARLY (est.)

min

max

$214730K

$303140K

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What You Should Know About EDA Design Flow Development Engineer, Intel

Join Intel as an EDA Design Flow Development Engineer in Austin, Texas, and become a vital part of the team that drives Moore's Law forward! In this exciting role, you will collaborate closely with the Design Technology Platform (DTP) team to maximize the value of our technology offerings through Design Technology Co-Optimization (DTCO). You’ll be responsible for architecting, executing, and delivering cutting-edge EDA design flows that span the entire design spectrum from RTL to GDS. Your contributions will directly impact both our technology lead vehicle designs and various product designs, ensuring that we're effectively meeting the demands of high-volume manufacturing. We're looking for someone who thrives in a fast-paced environment and is highly skilled in EDA tools and design flow execution. If you have experience developing EDA tools and flows for digital or analog designs and a strong programming background, you'll fit right in with our innovative culture. You'll also enjoy working on exciting projects that not only advance technology but also enrich the lives of people globally. With a competitive salary range of $214,730 to $303,140, Intel also offers amazing benefits and a hybrid work model that supports a balanced lifestyle. If you’re ready to make an impact in the world of semiconductor manufacturing and design, this is the opportunity for you!

Frequently Asked Questions (FAQs) for EDA Design Flow Development Engineer Role at Intel

What are the primary responsibilities of the EDA Design Flow Development Engineer at Intel?

The EDA Design Flow Development Engineer at Intel is responsible for architecting, executing, and delivering the EDA design flow for all DTCO activities, including technology lead vehicle design, IP design, and product design. This role involves developing flows on top of reference flows from external EDA vendors and ensuring that these flows cover all aspects of design from RTL to GDS.