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Product Engineer - Design For Test (DFT)

Siemens EDA is a global technology leader in electronic design automation software. Our software tools enable companies around the world to develop new and highly innovative electronic products faster and more cost-effectively. Our customers use our tools to push the boundaries of technology and physics in order to deliver better products in the increasingly complex world of chip, board and system design.Position OverviewThe Tessent division seeks a highly motivated, creative, and energetic individual as Product Engineer, specializing in design-for-test (DFT) and test delivery at chip and system level. Tessent is the market and technology leader of automated tools for insertion of semiconductor design-for-test (DFT) structures, automatic test pattern generation (ATPG), embedded deterministic compression (EDT), memory built-in self-test (MBIST), logic built-in self-test (LBIST), diagnosis-driven yield analysis (DDYA), hierarchical DFT solutions such as Streaming Scan Network (SSN), and analog fault injection and test. This position presents a great opportunity to stay involved technically while getting exposure to marketing and interacting with sales.Responsibilities include but are not limited to:• Define and characterize new product capabilities needed to meet customer requirements• Work collaboratively with Tessent R&D to prototype, evaluate, and test new products and features within complex IC design flows• Lead beta programs and support beta partners• Drive product adoption and growth• Create and deliver in-depth technical presentations, develop training material, white papers, contributed articles, and application notes• Develop and review tool documentation such as user and reference manuals• Work with customers as well as Siemens EDA stakeholders such as regional application engineers, global support engineers, and marketing• Work through complex technical issues and independently create solutions and new methodologies• Present complex principles in simple terms to broad audiences• Collaborate and share information across team boundaries in written and spoken forms• Some travel, domestic and internationalJob QualificationsThe successful candidate will possess the following combination of education and work experience:• BS degree (or equivalent) in Electrical Engineering, Computer Science, Computer Engineering, or related field is required• Must have minimum 8 years of experience, including 3+ years of experience in DFT for complex ASICs / SOCs, including some of the following areas: Automatic test pattern generation (ATPG), internal scan, embedded scan compression (EDT), packetized test delivery (SSN), memory built-in self-test (MBIST), logic built-in self-test (LBIST), IEEE 1687 IJTAG, analog design and simulation, hierarchical DFT implementation• Must have industry experience with DFT tools, preferably Tessent tool suite such as TestKompress, SSN, IJTAG, In-system Test• Able to architect Design for Test solution for every aspect of complex IC SoC design, including but not limited to hierarchal or tiled designs, designs with multiple power domains and high-speed IO IP• Industry experience with inserting scan, running ATPG and debugging fault coverage• Industry experience with the application of logic test patterns on Automatic Test Equipment (ATE) and creation of test program• Knowledge of IG-XL, Smartest8, Python or bench environments for production test or characterization• Exposure to one or more adjacent IC disciplines such as the following a plus:• RTL coding and verification using Verilog/SystemVerilog/VHDL• Synthesis and timing analysis• Place and route• Advanced IC packaging• DFT and test for embedded IP cores• Failure diagnosis• ATE use / test program development• Candidate should be high energy, curious individual, self-motivated to learn new DFT methodologies and technologies• Able to work as individual contributor and lead technical activities of junior engineers• Strong problem-solving, reasoning and deduction skills and the ability to analyze and debug complex design and simulation issues• Proficiency in LINUX and Windows environments• Proficiency in a scripting language like TCL (preferred) or Python• Excellent written and spoken English language communication skills• Excellent organizational skills• Nice to have skills:• Knowledge of HSIO functional interfaces such as PCIe or USB and their usage for DFT• Knowledge of functional verification techniques using UVM, PSS, emulators and VIP• Experience with sensors/monitors for IC designs that provide process, voltage, temperature, and other monitoring• Experience with application of patterns in a System Level Test (SLT) environment• Industry experience with FPGA design development and prototyping• Knowledge of data bases, visualization tools and packages• Location can be remote or hybrid in North America, or in-office at one the following Tessent locations:• Wilsonville (Oregon), Ottawa (Canada), Saskatoon (Canada), Fremont (California)Why us?Working at Siemens Software means flexibility - Choosing between working at home and the office at other times is the norm here. We offer great benefits and rewards, as you'd expect from a world leader in industrial software.A collection of over 377,000 minds building the future, one day at a time in over 200 countries. We're dedicated to equality, and we welcome applications that reflect the diversity of the communities we work in. All employment decisions at Siemens are based on qualifications, merit, and business need. Bring your curiosity and creativity and help us shape tomorrow!Siemens Software. Transform the EverydayThe salary range for this position is $151,300 to $272,400 and this role is eligible to earn incentive compensation. The actual compensation offered is based on the successful candidate’s work location as well as additional factors, including job-related skills, experience, and relevant education/training. Siemens offers a variety of health and wellness benefits to employees. Details regarding our benefits can be found here: www.benefitsquickstart.com. In addition, this position is eligible for time off in accordance with Company policies, including paid sick leave, paid parental leave, PTO (for non-exempt employees) or non-accrued flexible vacation (for exempt employees).#LI-EDA#LI-EW1#LI-HYBRIDEqual Employment Opportunity StatementSiemens is an Equal Opportunity and Affirmative Action Employer encouraging diversity in the workplace. All qualified applicants will receive consideration for employment without regard to their race, color, creed, religion, national origin, citizenship status, ancestry, sex, age, physical or mental disability unrelated to ability, marital status, family responsibilities, pregnancy, genetic information, sexual orientation, gender expression, gender identity, transgender, sex stereotyping, order of protection status, protected veteran or military status, or an unfavorable discharge from military service, and other categories protected by federal, state or local law.Reasonable AccommodationsIf you require a reasonable accommodation in completing a job application, interviewing, completing any pre-employment testing, or otherwise participating in the employee selection process, please fill out the accommodations form by clicking on this link Accommodation for disability form. If you’re unable to complete the form, you can reach out to our AskHR team for support at 1-866-743-6367. Please note our AskHR representatives do not have visibility of application or interview status.EEO is the LawApplicants and employees are protected under Federal law from discrimination. To learn more, Click here.Pay Transparency Non-Discrimination ProvisionSiemens follows Executive Order 11246, including the Pay Transparency Nondiscrimination Provision. To learn more, Click here.California Privacy NoticeCalifornia residents have the right to receive additional notices about their personal information. To learn more, click here.
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What You Should Know About Product Engineer - Design For Test (DFT), Siemens

Siemens EDA is searching for a passionate and skilled Product Engineer with a focus on Design For Test (DFT) to join our dynamic team in Wilsonville, OR. At Siemens, we pride ourselves on leading the charge in electronic design automation software, empowering companies globally to innovate faster and more cost-effectively. As a Product Engineer in the Tessent division, you will play a critical role in enhancing our cutting-edge automated tools for semiconductor DFT, including techniques such as automatic test pattern generation (ATPG) and embedded deterministic compression (EDT). Your responsibilities will be vast, from defining new product capabilities that align with customer requirements to collaborating closely with R&D teams to prototype and test new features within intricate IC design flows. You’ll also engage in beta programs, drive product adoption, and deliver compelling technical presentations. This role isn't just about the technicalities; it also allows for significant interaction with marketing, sales, and customers, fostering a complete understanding of our product ecosystem. If you have a solid background in DFT, are excited about engaging with the latest methodologies, and enjoy taking initiative, this position offers an incredible opportunity for growth while working alongside industry pioneers!

Frequently Asked Questions (FAQs) for Product Engineer - Design For Test (DFT) Role at Siemens
What are the responsibilities of a Product Engineer - Design For Test at Siemens EDA?

As a Product Engineer - Design For Test at Siemens EDA, your key responsibilities include defining new product capabilities to meet customer needs, collaborating with R&D on prototyping and testing new product features, leading beta programs, and driving product adoption. You'll also create technical presentations and documentation, interact with customers and stakeholders, and develop innovative solutions for complex technical issues.

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What qualifications are required for the Product Engineer - Design For Test position at Siemens EDA?

To qualify for the Product Engineer - Design For Test role at Siemens EDA, candidates should hold a BS in Electrical Engineering, Computer Science, or related fields, along with a minimum of 8 years of experience in DFT for complex ASICs/SOCs. Experience with DFT tools, especially the Tessent tool suite, is essential, alongside strong problem-solving skills and proficiency in scripting languages.

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How does the Product Engineer - Design For Test role at Siemens EDA incorporate marketing and sales interactions?

The Product Engineer - Design For Test role at Siemens EDA encourages substantial interaction with marketing and sales teams. You'll engage in various activities, from leading beta programs to creating technical materials that support product adoption. This position gives you the chance to influence marketing strategies through customer insights and technical expertise.

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Can the Product Engineer - Design For Test position at Siemens EDA be done remotely?

Yes, the Product Engineer - Design For Test position at Siemens EDA can be done remotely or through a hybrid setup in North America. This flexibility allows you to balance professional commitments while maintaining a comfortable work-life arrangement.

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What kind of technical skills are expected for the Product Engineer - Design For Test at Siemens EDA?

Candidates for the Product Engineer - Design For Test position at Siemens EDA are expected to have extensive technical skills, including knowledge of DFT methodologies, proficiency in tools such as Automatic Test Equipment (ATE), and experience in scripting languages like TCL or Python. Furthermore, familiarity with adjacent IC disciplines is an added advantage.

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Common Interview Questions for Product Engineer - Design For Test (DFT)
How do you approach defining new product capabilities for DFT solutions?

When defining new product capabilities for DFT solutions, I start by gathering feedback from customers to understand their needs. I then collaborate with R&D to analyze current technologies and identify gaps. Prototyping potential features and conducting evaluations ensure that the capabilities align with customer expectations and market trends.

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Can you explain your experience with automatic test pattern generation (ATPG)?

In my experience with ATPG, I have implemented various strategies to optimize test patterns for complex ASIC designs. By utilizing algorithms that minimize test time while maximizing fault coverage, I've been able to enhance the test efficiency significantly, ultimately leading to improved yield and reduced production costs.

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What methods do you use for troubleshooting complex design issues?

For troubleshooting complex design issues, I first replicate the problem to understand its context. Employing systematic techniques like failure analysis and using debugging tools, I work through the issue methodically. It's important to document the process to identify patterns and develop lasting solutions.

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Describe how you would lead a beta program for new DFT tools.

Leading a beta program involves clear communication and strong project management. I outline objectives, set timelines, and coordinate with beta partners, providing them with comprehensive support. Regular feedback sessions help me gather insights, which are then integrated into refining the tool before its official release.

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How do you ensure successful collaboration with regional application engineers at Siemens EDA?

To ensure successful collaboration with regional application engineers, I maintain open lines of communication and establish regular check-ins. Sharing knowledge and best practices fosters a team environment where everyone feels valued. I also encourage them to provide feedback on customer interactions, which informs our product development.

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What strategies do you use to deliver technical presentations effectively?

To deliver technical presentations effectively, I focus on simplifying complex concepts using visuals and relatable analogies. Engaging the audience through questions and real-world examples keeps their attention. Preparing thoroughly allows me to handle inquiries confidently and ensure clarity throughout the presentation.

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How do you handle tight deadlines while ensuring quality in your work?

Handling tight deadlines requires effective time management and prioritization. I break down larger tasks into manageable parts and set milestones to track progress. By maintaining high standards for my work and focusing on essential deliverables, I’m able to meet deadlines without compromising quality.

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What do you believe is the future of Design For Test methodologies?

The future of Design For Test methodologies lies in automation and intelligence. As designs become increasingly complex, integrating AI to optimize test patterns and diagnostics will be pivotal. Additionally, embracing machine learning can enhance fault diagnosis and yield analysis, making testing more efficient and effective.

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Describe a challenge you've faced in a previous DFT project and how you overcame it.

In a previous DFT project, we encountered a significant issue with fault coverage that didn’t meet our expectations. To address this, I conducted a root cause analysis and involved team members from different disciplines. Collaboratively, we updated our ATPG strategies, which ultimately improved our fault coverage metrics significantly.

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How do you stay current with the latest tools and technologies in DFT?

Staying current with the latest DFT tools and technologies involves dedicating time to continuous learning. I subscribe to industry journals, participate in webinars, and attend conferences. Networking with peers also allows me to gain insights into best practices and emerging technologies that impact our field.

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Full-time, hybrid
DATE POSTED
December 15, 2024

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