This opportunity is for a Product Engineer in the Digital and Signoff Group (DSG) at Cadence. The Cadence Digital and Signoff Group will offer you a dynamic environment in which you will work with innovative R&D and Customer Engagement teams to influence the development of software tools for advanced chip design platforms. As Product Engineer, you will be a source of technical place and route expertise to Cadence customers and to R&D.
You are a motivated and energetic engineer with a deep understanding of ASIC design methodologies and of every stage of the RTL to GDSII flow.
You have proven hands-on experience with timing closure and PPA optimization at 16nm and below nodes.
You combine your deep understanding with strong analysis skills to debug customer problems and propose solutions, with an organized and coherent approach.
You are an excellent communicator.
Position Responsibilities:
Support Cadence products in the Digital and Signoff team.
Track and debug customer issues and work with R&D and release team on issue resolution.
Run design benchmarks and develop flows and solutions.
Position Requirements:
BS in EE with 4+ year experience or MS in EE with 2+ years of experience in Digital Implementation, either as a design engineer or as a product engineer
Strong understanding of VLSI physical design and timing analysis; familiarity with digital implementation challenges including clock tree synthesis, routing optimization and silicon signoff.
Experience with industry standard EDA tools in Synthesis, Physical design and Signoff at 16nm and below nodes.
Energetic team player with a passion for problem solving
Strong analysis skills with a track record to prove it
Strong communication skills (verbal and written)
Automation skills using Perl, Tcl and shell scripting
The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.
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If you're passionate about technology and eager to make a meaningful impact, consider joining Cadence as a Product Engineer in our vibrant Digital and Signoff Group (DSG) based in San Jose. At Cadence, we pride ourselves on fostering leaders and innovators who drive the future of technology. As a Product Engineer, you'll team up with our Research and Development and Customer Engagement teams to enhance advanced software tools for chip design. Your expertise in ASIC design methodologies and RTL to GDSII flows will be put to great use. With hands-on experience in timing closure and PPA optimization at nodes of 16nm and below, you'll analytically address customer challenges, providing solutions and effectively debugging issues. Your skills will shine as you run design benchmarks and refine our processes to elevate our product offerings. Strong communication is key in this role, as you'll be the technical bridge for our customers and R&D teams. If you have a BS in EE with over 4 years of experience or an MS in EE with at least 2 years in Digital Implementation, particularly in VLSI physical design and timing analysis, we want to hear from you. With a collaborative and energetic team environment, this is your opportunity to innovate while enjoying competitive compensation and benefits. Let’s solve what others can’t together!
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