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SoC Physical Design Engineer

Job Details:

Job Description: 

We are looking for a SoC Physical Design Engineer, who is ready to research, design, develop, and test lead Intel designs as we reimagine how to build SoCs at Intel and in the semiconductor industry. Our bold purpose as a company is to create world-changing technology that enriches the lives of every person on earth and this role is instrumental in furthering our mission to shape the future of technology.


Your responsibilities may include but not be limited to:

  • Performing physical design implementation of custom IP and SoC designs from RTL to GDS to create a design database that is ready for manufacturing.

  • Physical Synthesis, Floor planning, Place and Route, Clock Tree Synthesis with Synopsys and/or Cadence EDA tools.

  • Multiple Power Domain analysis and handling using standard Power Formats UPF or CPF.

  • Verification and Signoff including Formal Equivalence Verification, Static Timing Analysis, Reliability Verification, Static and Dynamic power integrity, Layout Verification, Electrical rule checking, Noise analysis and Structural Design checking.

  • Analyzes results and makes recommendations to fix violations for current and future product architecture.

  • Participating in the development and improvement of physical design methodologies and flow automation.

  • Driving performance optimization, including co-optimization, work with process teams, to create best-in-class designs.


The ideal candidate should exhibit behavioral traits that indicate:

  • Self-motivator with strong problem-solving skills.

  • Excellent interpersonal skills, including written, verbal, and presentation communications.

  • Attention to detail and organizational skills.

  • Ability to work as part of a team and collaborate in a high-paced atmosphere.

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position. Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

  • Bachelor's degree in electrical engineering, Computer Engineering or related field with 5+ years of relevant experience OR

  • Master's degree Electrical Engineering, Computer Engineering or related field with 3+ years of relevant experience

The relevant experience would include one of the following areas:

  • Physical synthesis, place and route, and clock tree synthesis with Synopsys or Cadence tools.

  • Static timing analysis constraint understanding and generation, clock stamping, and timing closure.

  • Multiple Power Domain analysis using standard Power Formats UPF or CPF.


Preferred Qualifications:

  • 6+ years of experience in physical design using industry EDA tools.

  • 7+ years of experience in backend design and/or integration

  • Product development and delivery on leading edge process nodes

  • Experience in Python/Perl/TCL programming languages

          

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location: 

US, Oregon, Hillsboro

Additional Locations:

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation.  Find more information about all of our Amazing Benefits here:

https://jobs.intel.com/en/benefits

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

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Average salary estimate

$168470 / YEARLY (est.)
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$139710K
$197230K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About SoC Physical Design Engineer, Intel Corporation

Are you ready to dive deep into the world of semiconductor technology? Intel is on the lookout for a passionate SoC Physical Design Engineer to join our dynamic team in Hillsboro, Oregon. In this pivotal role, you'll have the chance to research, design, and develop leading-edge SoC designs, shaping the future of technology. Your responsibilities will include everything from physical design implementation of custom IP and SoC designs to employing EDA tools like Synopsys and Cadence for tasks such as Physical Synthesis, Place and Route, and more. You’ll be the one making vital recommendations to fix any design violations and drive performance optimization. If you are a self-motivated individual with a knack for problem-solving and strong interpersonal skills, you might just be the perfect fit for this role! Our team thrives in a fast-paced atmosphere, and we value attention to detail and an innovative spirit. Join us in creating technologies that enrich the lives of people all over the world. If you hold a degree in Electrical or Computer Engineering and have 5+ years of relevant experience in physical design, we can’t wait to hear from you!

Frequently Asked Questions (FAQs) for SoC Physical Design Engineer Role at Intel Corporation
What are the responsibilities of a SoC Physical Design Engineer at Intel?

As a SoC Physical Design Engineer at Intel, your duties will encompass physical design implementation from RTL to GDS, utilizing industry-standard tools for Physical Synthesis and Place and Route. You'll perform verification and sign-off checks, optimize performance, and recommend fixes for design violations, all while participating in the development of physical design methodologies. This role is vital in achieving best-in-class designs.

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What qualifications do I need to apply for the SoC Physical Design Engineer position at Intel?

To apply for the SoC Physical Design Engineer position at Intel, you must possess at least a Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field along with 5+ years of relevant experience. Alternatively, a Master's degree with 3+ years of relevant experience will also suffice. Familiarity with physical synthesis and EDA tools is a must.

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What skills are important for a SoC Physical Design Engineer at Intel?

Key skills for a SoC Physical Design Engineer at Intel include strong problem-solving abilities, expertise with EDA tools like Synopsys and Cadence, and proficiency in multiple power domain analysis. Additionally, excellent communication skills and an ability to work collaboratively in a high-paced environment are essential for success in this role.

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What tools do SoC Physical Design Engineers at Intel typically use?

SoC Physical Design Engineers at Intel typically utilize EDA tools such as Synopsys and Cadence for tasks like physical synthesis, place and route, and clock tree synthesis. Knowledge of power format handling through UPF or CPF is also important for managing various power domains effectively.

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What is Intel's work model for the SoC Physical Design Engineer position?

Intel offers a hybrid work model for the SoC Physical Design Engineer position, allowing employees to split their time between working on-site at Intel's Hillsboro location and off-site. This flexible approach is designed to support a balanced work-life integration while maintaining productivity.

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Common Interview Questions for SoC Physical Design Engineer
Can you explain your experience with physical design using EDA tools?

When answering this question, provide specific examples of projects where you utilized EDA tools for physical design tasks. Mention specific tools you have used, such as Synopsys or Cadence, and describe how you approached challenges in physical synthesis and timing closure.

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What techniques do you use for static timing analysis?

In your response, discuss the techniques you've employed for static timing analysis, emphasizing your understanding of constraints and clock stamping. You can also mention how you handle timing closure and any tools you've used in the process.

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How do you approach power domain analysis in your designs?

Explain your methodology for handling power domain analysis, ideally referencing your use of UPF or CPF formats. Provide details about how you've optimized designs for multiple power domains in previous projects.

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What steps do you take for ensuring reliability verification?

Outline your process for reliability verification by discussing key checks you perform, such as static and dynamic power integrity assessments, layout verification, and electrical rule checking. Mention specific experiences where these checks were critical.

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Describe a challenging design problem you faced and how you tackled it.

Provide a specific example of a challenging design problem you encountered. Detail the steps you took to analyze the issue, the solutions you proposed, and the outcome. This will showcase your problem-solving skills and determination.

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How do you collaborate with team members in a high-paced environment?

Discuss your approach to collaboration in fast-paced settings, emphasizing your communication skills and teamwork strategies. Share experiences where effective collaboration led to successful project outcomes.

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What methods do you use for performance optimization in your designs?

Talk about the strategies you implement for performance optimization, such as co-optimization with process teams. Provide examples demonstrating how your optimization efforts resulted in notable improvements in design performance.

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Can you describe a time when a design violated electrical rules?

In your answer, recount a specific incident where you encountered design violations, explaining how you discovered the issue and the remediation steps you took to resolve it while ensuring compliance with electrical rules.

Join Rise to see the full answer
What programming languages are you familiar with, and how do you use them in your work?

Describe your proficiency in programming languages like Python, Perl, or TCL, and provide examples of how you've leveraged these skills to enhance design automation, script development, or other tasks related to physical design.

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Why do you want to work for Intel as a SoC Physical Design Engineer?

Craft a thoughtful response explaining your interest in Intel, touching on its commitment to innovation and technology. Express enthusiasm for contributing to cutting-edge projects and alignment with the company’s mission to enrich lives through technology.

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DATE POSTED
April 4, 2025

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