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Analog Design Engineer - job 1 of 2

Job Details:

Job Description: 

Job Description:

IPG/HSIO is chartered to provide high speed serial link IPs to various internal and external SoCs within the Intel eco-system. Key IPs that we work on include PCI Gen6 and 80 Gbps Type-C USB PHYs.Analog Design Engineer is responsible for analog circuit Design and corresponding Sign-off Verification (Functional, reliability, Mixed-Signal Verification etc) for custom circuits like CTLE, DCO, DFE, Tx and high speed clocking along with leading teams of junior engineers, driving the closure of macro-blocks and IPs and mentoring junior engineers. What we are looking for is strong hands-on technical skill in high speed mixed-signal circuit design, initiative, ability to think in terms of the overall system and take the decisions necessary to build a better solution for Intel, ability to work in teams, ability to handle pressure and communicate both up and down the chain effectively.

Objectives of the position

  • Own and deliver the Circuit Design/Sign-off verification of high-speed serial link building blocks.
  • Groom the junior team members towards technical excellence, drive innovation in the team and harvest publications/patents.
  • Work with internal stakeholders such as mask design for circuit implementation and logic design to design the analog/digital interface
  • Continuously drive the Turnaround time, robustness of circuit design and area/power of IPs.
  • Drive Post-silicon electrical validation, post silicon debug and high-volume manufacturing support for the IPs.Desired Competencies and Experiences:
  • Experience in working with cutting edge silicon technologies.
  • Deep understanding of Circuit design/ physical design of Analog Designs on advanced process technologies.
  • Expertise on high speed serial link design. Hands-on experience in blocks like Continuous Time Linear Equalizer (CTLE), Digitally Controlled Oscillator (DCO), Decision Feedback Equalizer (DFE), NRZ/PAM-3/4 Transmitter and high speed clocking.
  • Expertise on Reliability aware design and familiarity with Aging and RV tools. Ability to design floor plan and routing in Layout.
  • Good grasp on Industry standard tools such as Cadence design Environment (ADEXL or Virtuoso) Knowledge of DRC, LVS, and post-layout extraction tools etc.
  • Familiarity with RTL behavioral coding and simulations, timing extractions of custom blocks
  • Strong communicator and proven leadership experience, self-driven, proactive nature to own and deliver high quality end to end Analog designs
  • Fast learner, good problem-solving skills, multitasking ability and attention to quality and detail.
  • Experience with MATLAB and system runs will be a major plus.

Qualifications:

Education:BS/MS - EE/CS and 10+ Years of industry experience.

          

Job Type:

Experienced Hire

Shift:

Shift 1 (India)

Primary Location: 

India, Bangalore

Additional Locations:

India, Hyderabad

Business group:

IP Engineering Group's (IPG) vision Build IPs that power Intel's leadership products and power our customer's silicon. We want to attract & retain talent who get joy in building high quality IP and share our core belief that IP is fundamental to transforming Intel's silicon design process. IPG's guiding principles will be ensuring Quality (Zero Bugs), Customer Obsession (Delight our Customers) and structured Problem Solving. We are a fearless organization transforming IP development.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$125000 / YEARLY (est.)
min
max
$100000K
$150000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About Analog Design Engineer, Intel

Are you an Analog Design Engineer looking to make your mark in a dynamic team at Intel? Based in the vibrant tech capital of Bangalore, India, you'll find an exhilarating opportunity with the IPG/HSIO team. This skilled group is dedicated to creating high-speed serial link IPs that power some of the most advanced SoCs in the industry, including cutting-edge PCI Gen6 and 80 Gbps Type-C USB PHYs. In this role, you'll take charge of designing analog circuits and ensuring their successful sign-off verification, including functional testing and reliability checks. Your expertise will shine as you lead a team of junior engineers, nurturing their skills while driving innovation and quality in our designs. What we seek is someone with a solid foundation in high-speed mixed-signal circuit design, an ability to think holistically about system solutions, and the knowledge to work collaboratively with various internal stakeholders. Your leadership skills will be essential as you guide the team through the excitement of developing novel IPs, focusing on performance, efficiency, and robustness. If you have experience with advanced silicon technologies, understand the nuances of high-speed serial link design, and are well-versed in tools like Cadence, we want to hear from you! This is more than just a job; it’s a chance to contribute to game-changing technologies that will help shape the future. Join us in making a difference at Intel, where your passion and skills will be valued and nurtured.

Frequently Asked Questions (FAQs) for Analog Design Engineer Role at Intel
What are the responsibilities of an Analog Design Engineer at Intel?

As an Analog Design Engineer at Intel, you will be responsible for the design and verification of analog circuits within high-speed serial link IPs. This includes ensuring a successful sign-off verification process for custom circuits and leading a team of junior engineers. Your role will entail collaborating with cross-functional teams, driving innovation, and maintaining high standards in circuit design. Furthermore, you'll engage in post-silicon validation and support to ensure the robustness of our designs.

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What qualifications are required for the Analog Design Engineer position at Intel in Bangalore?

To qualify for the Analog Design Engineer position at Intel in Bangalore, you should possess a BS or MS in Electrical Engineering or Computer Science, along with at least 10 years of industry experience. Expertise in high-speed mixed-signal circuit design, knowledge of advanced silicon technologies, and familiarity with industry standard tools such as Cadence are essential. Proven leadership abilities and strong communication skills will also be important in this dynamic role.

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What skills are essential for success as an Analog Design Engineer at Intel?

Success as an Analog Design Engineer at Intel requires a strong background in high-speed analog circuit design and familiarity with mixed-signal verification. You should possess hands-on expertise with components like Continuous Time Linear Equalizers (CTLE) and Decision Feedback Equalizers (DFE), as well as a solid understanding of reliability-aware design. Strong problem-solving capabilities, attention to detail, and the ability to work under pressure will also contribute to your effectiveness in this role.

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How does Intel support the professional growth of Analog Design Engineers?

Intel is committed to the professional growth of its Analog Design Engineers by providing opportunities for mentorship and skill development. In your role, you will take on leadership responsibilities, guiding junior engineers and fostering an environment of innovation. Additionally, Intel encourages publication and patenting initiatives as a means to share your expertise and contribute to the engineering community.

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What makes the Analog Design Engineer role at Intel unique?

The Analog Design Engineer role at Intel is unique because it combines cutting-edge technology with the opportunity to work on high-impact projects that shape the future of silicon design. You’ll not only work on advanced high-speed serial link IPs but also lead a team dedicated to driving excellence and innovation. This position offers a dynamic workplace and the chance to collaborate with various stakeholders, enhancing your experiences in design and validation.

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Common Interview Questions for Analog Design Engineer
Can you explain your experience with high-speed mixed-signal circuit design?

In your response, share specific examples from your past roles, focusing on particular circuits you've designed, such as CTLEs or DCOs. Discuss challenges you faced and how you resolved them, highlighting your technical skills and problem-solving capabilities.

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How do you ensure the reliability of your circuit designs?

Discuss your approach to reliability-aware design. Mention techniques you've used to assess reliability, tools for verification, and any experience with aging and RV tools. Highlight how you incorporate user requirements and feedback to inform your designs.

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What tools do you prefer for circuit design and why?

Share your preferred tools for analog design, such as Cadence design environments like ADEXL or Virtuoso. Explain your familiarity with these tools, how they facilitate aspects like DRC and LVS, and your overall process.

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Describe a project where you led a team through a complex design challenge.

Provide a narrative of a specific project, outlining the complexities and your leadership approach. Focus on how you guided your team through challenges, fostered collaboration, and drove the project toward successful completion.

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How do you stay updated with advancements in silicon technology?

Talk about the resources you rely on to keep current, such as industry publications, conferences, and networking with peers in the field. Emphasize your commitment to continuous learning and how you apply new knowledge to your work.

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Can you discuss your experience with post-silicon validation?

Outline your past experiences with post-silicon validation processes, describing specific methodologies you've used. Highlight how you've contributed to debugging and ensuring the performance of designs in a manufacturing context.

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How do you approach multitasking when managing multiple projects?

Share your strategies for effective multitasking, such as prioritization, time management techniques, and tools you use to keep organized. Discuss how you ensure quality and meet deadlines across projects.

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What strategies do you employ to mentor junior engineers?

Discuss your philosophy on mentorship, providing examples of how you've successfully trained and developed junior engineers. Highlight techniques you use to instill confidence, technical knowledge, and teamwork.

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Describe a situation where you faced pressure in a project. How did you handle it?

Provide a specific example of a high-pressure situation, detailing the context and your response. Focus on your decision-making process, how you maintained focus, and the outcome of your actions.

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What techniques do you use to drive innovation within your team?

Talk about your approach to fostering a culture of innovation, including brainstorming sessions, encouraging risk-taking, and how you utilize feedback. Mention any initiatives you've led that resulted in significant innovation.

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MATCH
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BADGES
Badge ChangemakerBadge Diversity ChampionBadge Flexible CultureBadge Global CitizenBadge Work&Life Balance
CULTURE VALUES
Inclusive & Diverse
Rise from Within
Mission Driven
Diversity of Opinions
Work/Life Harmony
Growth & Learning
Transparent & Candid
Customer-Centric
BENEFITS & PERKS
Snacks
Onsite Gym
Family Coverage (Insurance)
Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Resources
Life insurance
Disability Insurance
Health Savings Account (HSA)
Flexible Spending Account (FSA)
Learning & Development
Paid Time-Off
401K Matching
Maternity Leave
Paternity Leave
FUNDING
DEPARTMENTS
SENIORITY LEVEL REQUIREMENT
TEAM SIZE
EMPLOYMENT TYPE
Full-time, hybrid
DATE POSTED
April 17, 2025

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