Senior Engineer - Silicon Physical Design (Italy based)

As a Senior Engineer - Silicon Physical Design at Axelera AI, you will oversee critical aspects of ASIC Physical Design, including synthesis, floorplanning, place and route, and timing analysis. Your role will also involve executing clock tree synthesis (CTS) and integrating various IPs, all while collaborating with different teams to drive project success.

To qualify for the Senior Engineer - Silicon Physical Design position at Axelera AI, you should have at least 10 years of experience in Physical Design, particularly from RTL to GDS. Expertise in leading EDA tools such as Primetime, Innovus, and Design Compiler, along with strong scripting skills in Python or Tcl, are highly recommended.

Candidates for the Senior Engineer - Silicon Physical Design role at Axelera AI should be well-versed in several EDA tools, including Primetime, StarRC, Genus, Innovus, Design Compiler, and Calibre. Familiarity with these tools will enable you to execute effective design and verification processes.

Relocation is not mandatory to apply for the Senior Engineer - Silicon Physical Design position at Axelera AI. We offer a hybrid or remote setup, and we are also open to relocating candidates to cities like Bologna, Florence, or Milan if desired.

At Axelera AI, you can expect a vibrant, inclusive company culture that values creativity and innovation. We prioritize collective ownership and responsibility, fostering an environment where all team members are encouraged to contribute and celebrate their diversity.

Timing closure is crucial in Physical Design as it ensures that all data signals arrive at the destination within the specified time constraints. In preparation for your interview, emphasize your strategies for achieving timing closure and any tools you've used, such as Primetime or Genus, to optimize this process.

Discuss your extensive experience with synthesis, detailing specific projects or challenges you've faced. Outline how your background in using tools like Design Compiler or Innovus allowed you to optimize designs effectively, ensuring they achieved the expected performance metrics.

In your response, mention your approach to debugging within Physical Design contexts. Discuss specific tools you’ve utilized, like Calibre for DRC checks, and illustrate an instance where your problem-solving skills led to successfully resolving a design issue.

Clock tree synthesis (CTS) is key to minimizing clock skew and delay, central to achieving timing closure. When preparing for your answer, highlight your familiarity with CTS methods and specific challenges you’ve encountered, along with how you overcame them to ensure timing integrity.

Share a detailed example of a project where you successfully integrated various IPs, such as memories and analog IPs. Emphasize your collaboration with RTL and verification teams, detailing pertinent tools and techniques you used for smooth integration.

To ensure high quality in Physical Design deliverables, talk about your systematic approach to verification, using tools like StarRC for accuracy checks. Highlight your emphasis on cross-verification with architecture and RTL teams to maintain high standards.

Discuss how automation streamlines your workflow in Physical Design tasks, such as through scripting in Python or Tcl. Give examples of automation processes you've implemented that increased efficiency or reduced errors in design implementation.

Talk about the physical verification tools you've used extensively, such as Calibre. Share how using these tools helped you identify design rule violations early in the process, thus refining your designs before the final signoff.

In your answer, consider discussing your proactive approach to collaborating with cross-functional teams and providing input on best practices in design methodologies. Mention specific examples where your suggestions led to improved methodologies in past roles.

Explain how staying updated is essential for a Senior Engineer - Silicon Physical Design. Share your methods, such as following industry publications, attending conferences, or participating in relevant online forums to keep abreast of emerging trends and technologies in the semiconductor industry.