Job details

Power Integrity Engineer

Get a free resume review

Job Details:

Job Description:

Are you passionate about ensuring high-quality power integrity solution in cutting-edge heterogeneous SoCs for high-power discrete graphics products? Disrupting the industry with your innovation? Working with leading graphics hardware engineers on Intel's latest GPU/CPU architecture? Do you love collaborating with diverse teams to help achieve best-in-class visual experiences that enable users to immerse themselves in a new visual future? Then Intel's Power and Signal Integrity Group within Graphics Organization has opportunities for you.

If you join the team, you will develop hardware and graphics solutions for Intel products including the newest IPs targeted at next gen GPUs. You will have the opportunity to participate in enabling technologies in the areas of high-power, high-performance design, power integrity analysis and design solution. We are a winning team with a clear vision of delivering competitive and cutting-edge products, and we care about building the best products and the best skills for our team.

This Power Integrity Engineer position involves research, pathfinding, implementation, analysis, validation and sign-off of power distribution network (PDN) including monolithic and heterogenous SoCs, package substrate, PCB and VRM. You will work with multi-functional teams to drive the development of advanced droop mitigation schemes, develop PI methodology and automation, quantify benefits of various circuit schemes through end-to-end PDN simulations, provide design guidelines and requirements to platform, package and SoC/IP teams ensuring robust integrations.

Additional areas of responsibility for this role include, but not limited to the following:

Develop and analyze power delivery networks including 2D and 3D model extraction and noise analysis across die/C4 bumps, silicon, package, sockets, and boards
Collaborate with the silicon integration team, die floor planners, package and PCB design teams to optimize the on-die decoupling partitions and implement the package/PCB decoupling scheme and voltage regulation for package/die
Define power grid specification and power and area targets to achieve the best balance of power integrity and performance
Derive platform level specifications from silicon specifications, ensure package/platform pathfinding to converge on feature set/form factor, and VR performance, characterization
Performs measurements to characterize power noise profile across frequency, ground bounce, and other key metrics to verify power delivery network after design and correlate back to pre-silicon models
Adhere to project timelines and deliver high-quality work within specified deadlines

The ideal candidate must exhibit good communication skills and ability to document and share findings with others

Qualifications:

Qualifications:

You must possess the below minimum qualifications to be initially considered for this position.
Preferred qualifications in addition to the requirements and are considered a plus factor in identifying top candidates.

Minimum Qualifications:

Bachelor's degree with 5+ years, masters with 3+ years of experience in Electrical or Computer Engineering or related field, which must include:
Knowledge of Silicon, Package and PCB PDN design practices
Good understanding of various droop mitigation schemes, Verilog level modeling, On-chip PDN and circuit techniques
Expertise in circuit simulation with Spice, ADS and EM extractions with commercially available solvers from Ansys, Cadence, Synopsys and Keysight
Scripting skills in Python/tcl

Preferred Qualifications:

Design, modeling and analysis experience of on-chip droop mitigation, LDO techniques, die/package/PCB PDN
Experience with transmission line theory and electromagnetic field theory
Package and PCB design tools from Cadence and Mentor
Power converter topologies and control schemes
PhD in Electrical or Computer Engineering or related field.

Job Type:

Experienced Hire

Shift:

Shift 1 (United States of America)

Primary Location:

US, California, Folsom

Additional Locations:

US, Arizona, Phoenix, US, California, San Diego, US, California, Santa Clara, US, Oregon, Hillsboro, US, Texas, Dallas

Business group:

The Client Computing Group (CCG) is responsible for driving business strategy and product development for Intel's PC products and platforms, spanning form factors such as notebooks, desktops, 2 in 1s, all in ones. Working with our partners across the industry, we intend to deliver purposeful computing experiences that unlock people's potential - allowing each person use our products to focus, create and connect in ways that matter most to them. As the largest business unit at Intel, CCG is investing more heavily in the PC, ramping its capabilities even more aggressively, and designing the PC experience even more deliberately, including delivering a predictable cadence of leadership products. As a result, we are able to fuel innovation across Intel, providing an important source of IP and scale, as well as help the company deliver on its purpose of enriching the lives of every person on earth.

Posting Statement:

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.

Position of Trust

N/A

Benefits:

We offer a total compensation package that ranks among the best in the industry. It consists of competitive pay, stock, bonuses, as well as, benefit programs which include health, retirement, and vacation. Find more information about all of our Amazing Benefits here:

https://intel.wd1.myworkdayjobs.com/External/page/1025c144664a100150b4b1665c750003

Annual Salary Range for jobs which could be performed in the US:

$139,710.00-$197,230.00

Salary range dependent on a number of factors including location and experience.

Work Model for this Role

This role will be eligible for our hybrid work model which allows employees to split their time between working on-site at their assigned Intel site and off-site. * Job posting details (such as work model, location or time type) are subject to change.

Average salary estimate

$168470 / YEARLY (est.)

min

max

$139710K

$197230K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About Power Integrity Engineer, Intel

Are you ready to take your career to the next level as a Power Integrity Engineer with Intel? Located in the sunny city of Folsom, California, this role gives you the unique opportunity to work on cutting-edge heterogeneous SoCs tailored for high-power discrete graphics products. If you've ever dreamed of contributing to groundbreaking innovations in the field of power integrity, now is your chance! Collaborate with some of the best graphics hardware engineers as you dive into Intel’s latest GPU and CPU architectures. You will be instrumental in crafting advanced hardware solutions and ensuring top-notch power delivery networks (PDNs) that not only meet but exceed industry standards. Your responsibilities will include developing and analyzing power delivery systems, optimizing decoupling partitions, and implementing voltage regulation schemes. With your expertise in circuit simulation and knowledge of PDN design practices, you’ll quantify the benefits of various circuit schemes and present your insights to multi-functional teams. At Intel, we believe in balancing performance with power integrity, and your role will be crucial in defining specifications that ensure both. Join a team that celebrates innovation, timely project completions, and continuous learning. If you thrive in a collaborative environment and are eager to drive powerful technology forward, this Power Integrity Engineer position at Intel might be the perfect fit for you!

Frequently Asked Questions (FAQs) for Power Integrity Engineer Role at Intel

What are the responsibilities of a Power Integrity Engineer at Intel?

As a Power Integrity Engineer at Intel, your primary responsibilities include the research and implementation of power distribution networks (PDNs) for advanced heterogeneous SoCs. You will collaborate with various teams, including silicon integration and PCB design, to develop droop mitigation schemes and establish comprehensive design guidelines. Your role entails performing simulations to analyze power delivery systems, characterizing noise profiles, and ensuring that all components work seamlessly together to optimize performance.