Job details

Staff DFT Engineer

Get a free resume review

Join the leading chiplet startup! As an Eliyan Staff DFT Engineer, you will be working at a fast paced early stage startup creating technologies that fuel tomorrow’s chiplet based systems with best-in-class power, area, manufacturability, and design flexibility. You will be defining and implementing scan, BIST, 1149, and reporting coverage. You will work with a cross-functional team of industry experts that operate from first principles, innovate and push the envelope to create high-volume and high-performance manufacturable products. We offer a fun work environment with excellent benefits.

Key Responsibilities:

Define DFT strategy, methodologies, and implementation plan
Implement DFT features in RTL for digital and analog blocks
Run ATPG and create and simulate DFT vectors
Generate and insert TAP/JTAG interface for chiplet/IP designs
Work with Analog/Mixed Signal (AMS) teams to ensure DFT coverage for high-speed interfaces
Work with circuit architects on boundary scan and loopback capabilities
Prepare vectors for post-silicon bring up (DVT vs. ATE)
Report status of DFT test coverage and mitigation strategy to narrow down holes

Minimum Qualifications:

General knowledge of digital and AMS circuit design techniques
Broad knowledge of DFT methodologies and tools
Proficient in Verilog/System Verilog and scripting
Ability to work collaboratively with cross functional team
Prepare test vectors and collateral for ATE test team
BS EE or equivalent, with 6-9 years of experience

Ideal Qualifications:

Breadth of expertise in MBIST, JTAG, IEEE1500, 1149, 1687, 1838
Provide balanced tradeoffs of test time vs complexity vs coverage
Ability to create DFT collateral for IP
3+ experience with Siemens Tessent MBIST, Scan Insertion and SSN flow
MS/PhD EE or equivalent, with 6-9 years of experience

Average salary estimate

$135000 / YEARLY (est.)

min

max

$120000K

$150000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About Staff DFT Engineer, Eliyan

Join the leading chiplet startup! As a Staff DFT Engineer at Eliyan, located in the vibrant Bay Area, you will dive headfirst into the exciting world of chiplet-based systems that promise the best in power, area, manufacturability, and design flexibility. In this fast-paced early-stage startup, you'll get the chance to define and implement scan, BIST, 1149 standards, and reporting coverage. You'll collaborate with a cross-functional team filled with industry veterans who love to innovate and push the limits to create high-volume, high-performance products. It's not just a job; it's a fun work environment with fantastic benefits that ensure you can thrive in your role. Your key responsibilities will include defining the DFT strategy and methodologies, implementing DFT features in RTL for various digital and analog blocks, and preparing vectors for post-silicon bring up. You’ll also have the opportunity to work closely with AMS teams to ensure adequate DFT coverage and engage with circuit architects to refine boundary scan capabilities. To thrive in this role, you'll need a general knowledge of digital and AMS circuit design techniques, along with proficiency in Verilog/System Verilog and scripting. If you have a balance of test time, complexity, and coverage expertise, this position is a great match for you. Bring your skills to Eliyan and take part in shaping the future of technology!

Frequently Asked Questions (FAQs) for Staff DFT Engineer Role at Eliyan

What are the core responsibilities of a Staff DFT Engineer at Eliyan?

As a Staff DFT Engineer at Eliyan, you will be responsible for defining the DFT strategy and methodologies, implementing DFT features in RTL for both digital and analog blocks, and generating ATPG vectors. Your role will also involve collaborating with cross-functional teams on challenges related to high-speed interfaces, reporting on DFT test coverage, and preparing vectors for post-silicon bring up.