Job details

Senior Verification Engineer

Get a free resume review

Cambridge, UK | Full-time or Part-time | Permanent | Hybrid

Salary: £65,000 to £80,000 DOE

We will also consider part-time applications for this role. Please indicate your preferred working schedule in your cover letter.

About us

Riverlane’s mission is to make quantum computing useful, sooner. From advances in material science to complex chemistry simulation for drug design and discovery, quantum computers will help solve some of the world’s most important challenges. Riverlane is building the quantum error correction stack, Deltaflow, to make this happen. It’s a complex problem that requires a range of skills, talent and passion.

We recently raised $75M in Series C funding to accelerate our cutting-edge R&D in quantum error correction (QEC), and are partnering with many of the world’s leading quantum hardware providers and government agencies to make fault-tolerant quantum computing a reality. We’re making remarkable progress and growing fast. 

About the role

You will work with our talented team of hardware designers and embedded software engineers to produce a fully verified, trusted and performant solution. With full visibility of the entire stack, you will own everything verification related. As a Senior Verification Engineer at Riverlane, you will:

Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.

Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.

Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way...

What you will do

Proactively work with designers and architects to define verification plans based on design specifications. You will own, define and track detailed test plans for different blocks and system level.

Implement scalable testbenches, including checkers, reference models and coverage groups in SystemVerilog. You will implement self-testing, directed and random tests.

Maintain the design verification environment, keeping track of regression, coverage metrics and bugs.

You do not need a background in quantum computing! You will learn this along the way...

What we need

Demonstrable commercial experience in functional verification, including ownership of verification planning and strategy.

A proactive and collaborative person who actively shares feedback and who can independently define the scope of work.

Proven experience of testbench design with verification frameworks like UVM/OVM.

Knowledge of SystemVerilog assertion (SVA).

Exposure to different programming languages, such as C, C++ and Python

Even better if

You have formal verification experience

What you can expect from us

A comprehensive benefits package, including annual bonus scheme, private medical insurance, life insurance, a contributory pension scheme (and much more)

Equity so that our team can share in the long-term success of Riverlane

28 days annual leave (plus bank holidays) and enhanced family leave

A diverse work environment that brings together experts in many fields (including software and hardware development, quantum information theory, physics, maths and many more) and over 20 different nationalities

A learning environment that encourages individual, team and company growth and learning, including an annual training and conference budget

How to apply

Please upload a CV and cover letter by clicking 'Apply'. Your cover letter should explain why you are applying for the job and what skills and experience you can bring to the role.

We review CVs as we receive them and interview as soon as we have applications that look like a good match (usually within one week). We do not use closing dates. So, please apply as soon as possible to avoid missing out on this role. We advertised this role on 4th April 2025. If you have any queries, please contact jobs@riverlane.com.

Everyone is welcome at Riverlane. We are an equal opportunities employer and encourage applications from eligible and suitably qualified candidates regardless of age, disability, ethnicity, gender, gender reassignment, religion or belief, sexual orientation, marital or civil partnership status, or pregnancy and maternity/paternity.

Studies have shown that women tend to apply to jobs if they meet all or almost all of the requirements whereas men apply even if they meet only some of the requirements. If that sounds like you then please apply – we are happy to review your application and let you know if we think you might be a good fit.

If you need any adjustments made to the application or selection process so you can do your best, please let us know. We will be happy to help.

Riverlane Glassdoor Company Review

4.6

Riverlane DE&I Review

3.9

CEO of Riverlane

Steve Brierley

Approve of CEO

Average salary estimate

$72500 / YEARLY (est.)

min

max

$65000K

$80000K

If an employer mentions a salary or salary range on their job, we display it as an "Employer Estimate". If a job has no salary data, Rise displays an estimate if available.

What You Should Know About Senior Verification Engineer, Riverlane

Riverlane is on the lookout for a passionate and experienced Senior Verification Engineer to join our dynamic team! Based in Cambridge, UK, this role offers the flexibility of either full-time or part-time arrangements. Salary ranges from £65,000 to £80,000 depending on experience, and we're open to discussing your preferred working schedule in your application. At Riverlane, our mission is to harness the power of quantum computing to tackle some of the world’s most pressing challenges, from material science breakthroughs to drug discovery. In this pivotal role, you'll collaborate closely with talented hardware designers and embedded software engineers to ensure our solutions are fully verified and perform exceptionally. You’ll have the opportunity to define verification plans based on design specifications, implement scalable testbenches in SystemVerilog, and maintain a robust verification environment. Don’t worry if you don’t have a background in quantum computing—a willingness to learn is all you need! If you’re looking to make a significant impact in a rapidly evolving field while being part of a diverse and innovative team, we’d love to hear from you.

Frequently Asked Questions (FAQs) for Senior Verification Engineer Role at Riverlane

What are the primary responsibilities of a Senior Verification Engineer at Riverlane?

As a Senior Verification Engineer at Riverlane, you'll primarily focus on defining and implementing verification plans, creating scalable testbenches in SystemVerilog, and maintaining the design verification environment. You'll proactively collaborate with designers and architects to ensure comprehensive coverage and thorough verification, thereby playing a critical role in the development of quantum error correction technology.