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Senior Principal Circuit Design Engineer (High Speed IO)

DescriptionInvent the future with us.Recognized by Fast Company’s 2023 100 Best Workplaces for Innovators List, Ampere is a semiconductor design company for a new era, leading the future of computing with an innovative approach to CPU design focused on high-performance, energy efficient, sustainable cloud computing.By providing a new level of predictable performance, efficiency, and sustainability Ampere is working with leading cloud suppliers and a growing partner ecosystem to deliver cloud instances, servers and embedded/edge products that can handle the compute demands of today and tomorrow.Join us at Ampere and work alongside a passionate and growing team — we’d love to have you apply. Come invent the future with us.About the role:We are looking for an experienced High Speed IO VLSI Design Engineer to join a small but growing Processor Design group, advancing the art of high-performance IO design.Ideal candidates will channel their creativity to develop designs in conjunction with system, logic and physical design architects to deliver cutting edge IO interfaces. They will have design flexibility and end-to-end ownership responsibilities to make highly visible contributions.What you’ll achieve:• Evaluate and drive architecture choice of state-of-the-art IO circuit IPs from various IP vendors for use in a cloud-computing server SOC in bleeding edge process technology nodes• Role would transition to designing and developing custom IP in-house to meet specifications based on customization needs vs. vendor IP availability• Act as a technical liaison to communicate needs to vendors, and assess vendor IP for design and schedule risks• Custom IP development would encompass architecture definition through implementation, post-silicon validation and productization• Understand system needs and assess specifications for IP requirements, and provide feedback to architecture team on design feasibility• Work with logic, physical design and packaging teams to develop a robust integration strategy of IP to ensure a successful product• Develop validation strategies to ensure IP circuit and overall system function as designed in post-silicon lab measurement and characterization environmentAbout you:• Strong understanding of analog and mixed signal design techniques as well as SI/PI concepts of SerDes and IO IPs• Demonstrated hands on project design, implementation and delivery experience• Experience with cadence design suite for schematic, layout and Spice simulations• Experience with physical design integration and optimization, functional debug and post-layout netlists• Electrical or Computer Engineering - Bachelor's degree & 12 years of related experience; or Master's degree & 8 years; or PhD & 5 yearsWhat we’ll offer:At Ampere we believe in taking care of our employees and providing a competitive total rewards package that includes base pay, bonus, equity, and comprehensive benefits. The full base pay range for this role is between $135,400 and $225,600, except in the San Francisco Bay Area where the range is between $146,300 and $243,800. We offer an annual bonus program tied to internal company goals and annual meritocratic equity awards that enable our employees to participate in the success of the company.Our benefits include health, wellness, and financial programs that support employees through every stage of life, with full benefits eligibility at 20 hours per week. Benefits highlights include:• Premium medical insurance, dental insurance, vision insurance, as well as income protection and a 401(k) retirement plan, so that you can feel secure in your health and financial future• Unlimited Flextime and 10+ paid holidays so that you can embrace a healthy work-life balance• A variety of healthy snacks, energizing espresso, and refreshing drinks to keep you fueled and focused throughout the dayThere is much more than compensation and benefits. At Ampere, we foster an inclusive culture that empowers our employees to do more and grow more. We are passionate about inventing industry leading cloud-native designs that contribute to a more sustainable future. We are excited to share more about our career opportunities with you through the interview process.#LI-TC#LI-HybridAmpere is an inclusive and equal opportunity employer and welcomes applicants from all backgrounds. All qualified applicants will receive consideration for employment without regard to race, color, national origin, citizenship, religion, age, veteran and/or military status, sex, sexual orientation, gender, gender identity, gender expression, physical or mental disability, or any other basis protected by federal, state or local law.

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What You Should Know About Senior Principal Circuit Design Engineer (High Speed IO), Ampere Computing

If you're passionate about innovation and eager to shape the future of computing, Ampere's Portland, OR team is looking for a Senior Principal Circuit Design Engineer specializing in High Speed IO. At Ampere, recognized in Fast Company's 2023 list of 100 Best Workplaces for Innovators, we focus on designing cutting-edge, energy-efficient semiconductors that meet the evolving demands of cloud computing. In this exciting role, you'll work within a dynamic Processor Design group, where your creativity will be key to developing advanced IO circuit designs. You will take on end-to-end ownership, allowing you to assess architecture choices and transition to custom IP development to meet specific requirements. Collaboration with system architects, logic, physical design, and packaging teams will be part of your daily routine as we aim to deliver optimal integration strategies. Your experience in analog and mixed signal design, along with your hands-on project experience, will facilitate validation strategies and ensure product success. At Ampere, you'll enjoy competitive compensation, a comprehensive benefits package, and an inclusive culture that supports your professional growth. Taken together, this positions you to make a highly visible contribution to the future of cloud-native designs. So come join us and let’s invent the future together!

Frequently Asked Questions (FAQs) for Senior Principal Circuit Design Engineer (High Speed IO) Role at Ampere Computing
What are the responsibilities of a Senior Principal Circuit Design Engineer at Ampere?

As a Senior Principal Circuit Design Engineer at Ampere, your main responsibilities include evaluating and driving architecture choices for IO circuit IPs, transitioning to the design and development of custom IPs in-house, serving as a technical liaison with vendors, and ensuring successful integration with logic, physical design, and packaging teams. You will also develop validation strategies to confirm the correctness of designs in real-world lab environments.

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What qualifications are required for the Senior Principal Circuit Design Engineer position at Ampere?

To qualify for the Senior Principal Circuit Design Engineer position at Ampere, candidates should have a Bachelor's degree in Electrical or Computer Engineering with at least 12 years of related experience, a Master's degree with 8 years, or a PhD with 5 years of relevant work. Additionally, strong knowledge of analog and mixed signal design techniques, as well as experience with Cadence design tools, is essential.

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How does Ampere support work-life balance for its Senior Principal Circuit Design Engineers?

Ampere is dedicated to supporting work-life balance for Senior Principal Circuit Design Engineers by providing unlimited flextime, over 10 paid holidays, and a variety of welfare benefits. This allows employees to manage their professional responsibilities while ensuring personal well-being and time for life outside of work.

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What is the work culture like for Senior Principal Circuit Design Engineers at Ampere?

The work culture at Ampere is inclusive and empowering, emphasized by our commitment to innovation and sustainability in cloud-native designs. Senior Principal Circuit Design Engineers will find themselves in a collaborative environment where creativity is encouraged, and contributions are valued, fostering both personal and professional growth within the organization.

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What benefits does Ampere offer to its Senior Principal Circuit Design Engineers?

Ampere offers a competitive total rewards package for Senior Principal Circuit Design Engineers that includes base pay ranging from $135,400 to $225,600, an annual bonus program, health insurance, a 401(k) retirement plan, and additional perks like healthy snacks and drinks at the workplace. These benefits help support employees' overall wellness and financial security.

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Common Interview Questions for Senior Principal Circuit Design Engineer (High Speed IO)
Can you describe your experience with high-speed IO design?

A great way to answer this question is by detailing specific projects where you worked on high-speed IO design. Describe the type of technology used, your contributions, and the results achieved. Highlight any challenges you overcame and tools you utilized, such as Cadence design suite.

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How do you evaluate and choose state-of-the-art IO circuit IPs?

Explain your methodology for evaluating IO circuit IPs, including criteria like performance, scalability, and vendor reputation. Provide examples of how you have successfully assessed IPs in past projects, discussing any frameworks or tools you employed in your evaluation.

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What strategies do you implement for post-silicon validation?

Discuss the importance of post-silicon validation and detail the strategies you have effectively used. This could include lab measurements, characterization methods, and how you ensure the design functions as intended within system architecture.

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Describe your experience with vendor relationships and how you manage communication in projects.

Focus on your experience acting as a liaison between your team and vendors. Describe how you ensure clear communication regarding needs, specifications, and feedback while also assessing vendor risks. Providing a specific example can illustrate your successful vendor management.

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Can you explain a time when you had to integrate diverse engineering teams?

For this question, share specific examples where you've collaborated with logic, physical design, and packaging teams. Highlight your role in facilitating successful integration strategies and any challenges faced along the way.

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What are your thoughts on the future of circuit design in cloud computing?

Use this opportunity to express your vision for the future of circuit design, particularly related to high-speed IO in cloud computing. Discuss emerging trends, the impact of technology advancements, and how those can shape designs that meet sustainability and performance goals.

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How do you ensure that your designs are energy-efficient?

Explain the methods and design strategies you use to achieve energy efficiency. This could involve optimization techniques, types of materials, and reviewing design architecture to ensure performance goes hand-in-hand with energy efficiency.

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What tools do you use for circuit design and simulation?

Provide a list of design tools and simulation software you are proficient with, emphasizing your experience with Cadence design suite. Discuss how these tools enhance your design workflow and ensure accuracy in your projects.

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How do you keep yourself updated with the latest advancements in circuit design technologies?

Share your strategies for staying current, such as attending workshops, reading industry publications, or participating in online forums. This demonstrates your commitment to continuous learning, which is valuable for the role.

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What does successful teamwork look like to you in an engineering project?

Discuss the qualities of effective teamwork, such as communication, respect, and collaboration. Provide examples of how you've fostered a positive team environment in previous projects and how that led to successful outcomes.

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Amphere Computing is a semiconductor company that manufactures ARM-based computer processors for cloud and edge servers. Amphere's products include hardware that support data storage, artificial intelligence and cloud infrastructure. The company i...

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March 21, 2025

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